All-
Which doc shows how slow/fast mode I2C boot clock is derived? If the CPU has a 100 MHz input reference clock, and the PLL is in bypass mode, how is 400 kHz derived?
Also we're assuming, based on other e2e discussion, that (i) BOOTMODE[8] determines the I2C boot output clock rate, with a value of 0 specifying fast mode, and (ii) using a value of 1 for this on the GPIO boot mode pins will not work and there is no plan to fix this with revised silicon.
Thanks.
-Jeff
Signalogic
