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XDATDLY=1 in McBSP1 of C6748 doesn't work for me

Joaquin Domingo
Prodigy 150 points

Configuring XDATDLY=1 in McBSP1 of a C6748 DSP I cannot get the 1-bit delay I need. It behave  like provoking an advance of 1 bit and  the bit  coinciding with FS forced to 1.

Is there any special consideration to use XDATDLY. I've used in C54 and C55 DSPs without any problem but with C6748 I can make it work.

Best Regards,

Joaquin

  • 0
    TI__Guru* 84110 points

    Joaquin,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    You may want to search this forum for XDATDLY and C6748 to see if anyone else has dealt with a similar issue.

    The XDATDLY field should cause the same functionality as shown in the TRM section 24.2.5.5.5 Figure 24-13 on page 1135.

    Are you looking at the signals with an oscilloscope or a logic analyzer?

    How does the waveform vary with the 3 different settings of 00, 01, and 10?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 150 points

    Hi Randy,

    I've read that section of the TRM.

    I'm looking at the signals with a logic analyzer, really 2 logic analyzers. The FS is generated internally. The program is run with an emulator Blackhawk USB560 v2.

    - With XDATDLY=00, I get 1st bit after the FS, as the TRM says.

    - With XDATDLY=01, I get 1 bit to the left instead to the right  (but the bit synchronized with FS is set to 1 always).

    - With XDATDLY=10,  I get a 2 bits to the left instead to the right  (but the bit synchronized with FS is set to 1 always and I lost 1 bit).

    Regards,

    Joaquin

  • 0 in reply to Joaquin Domingo
    Prodigy 150 points

    Hi Randy,

    Sorry, I was wrong, it's in this way:

    -  With XDATDLY=00, I get 1st bit synchronized with  the FS, as the TRM says.

    - With XDATDLY=01, I get 1 bit to the left instead to the right  (but the bit synchronized with FS is set to 1 always).

    - With XDATDLY=10,  I get a 2-bit delay to the right as the TRM says.

    Regards,

    Joaquin

  • 0 in reply to Joaquin Domingo
    TI__Guru* 84110 points

    Joaquin,

    A left shift as you describe cannot be done by any setting that I can think of. There must be something in your test data or your measurement method that is misleading.

    Use a scope or set the Logic Analyzer to high-speed sampling mode instead of XCLK sampling.

    Use test data that has a single 1 or a single 0 in it.

    If this device supports a loopback mode, try it and see if you can receive data properly.

    Connect the serial transmit data to the serial receive side and see if you can properly receive data.

    Regards,
    RandyP