AM335x RTC_PORz Timing Requirements

The RTC reset is not a function of the 32.768 kHz oscillator (OSC1) since RTC is initially sourced from the peripheral PLL operating in bypass mode immediately after power is applied to AM335x.  The Master Oscillator (OSC0) oscillator, which startes in about 1.5ms and operates at 19.2, 24, 25, or 26 MHz, is used as the Peripheral PLL reference clock after power-up.  This PLL will default to bypass mode which outputs the OSC0 reference clock divided by 29296.875 to the RTC.  If using a 24 MHz crystal, the RTC will initially be clocked at 819.2 Hz until software initializes the peripheral PLL to operate at 960 MHz.

So the RTC reset only needs to be held low for the OSC0 startup time plus a few RTC clock cycles after all power rails are valid.  This time could be as short as 20ms assuming OSC0 starts in 1.5ms.  The system designer is responsible for verifying the startup time of OSC0 across all operating conditions with the external crystal circuit being used in the product.

Regards,
Paul

I spent more time investigating your original question.  The minimum time requirement for holding RTC_PWRONRSTn low is not a function of the clock source.

RTC_PWRONRSTn must be held low at least 1ms after VDDS_RTC is valid to allow enough time for the internal LDO to produce a valid CAP_VDD_RTC source.  This is the only time requirement for RTC_PWRONRSTn since RTC_PWRONRSTn resets the RTC and activates a clock gating circuit that blocks the RTC clock until software has turned it back on.

RTC_PWRONRSTn must be held low until both VDDS_RTC and CAP_VDD_RTC are valid if you are using an external power source for CAP_VDD_RTC.

There should not be a problem if you follow the recommendations provided in SLVU551.

Regards,
Paul