My Set is as shown below
Platform: DM648 custom board
CCS5.5
SYS/BIOS 6.35
1) I Wanted to enable part of L2 as Cache. I did this thru' the GEL file(attached) and confirmed thru console messages.
Now when I check ROV and Register view , I get different results. Attached the snap shots.
ROV says that L2 Cache size 0k when the register value says that 64K (L2CFG=0x00010010)
But the GEL file is L2 settings are 3/4 SRAM . I am confused. Which one is correct?
I see no improvement in performance when Cache= 0 to 3/4 SRAM.
2) How can I use BCACHE APIs? Pls point to some docs.
3) Can I configure, enable/disable the Cache thru' SYS/BIOS XGCONF? I saw previous version CCS supports configuring Cache thru GCONF like below
How can I configure cache using XGCONF in CCS 5.5?
Best Regards
JK
