capture 1080P@60

Hi,

The changes are correct assuming you input is 16bit discrete sync with hsync/vsync style of capture.

Regards,

Brijesh

Brijesh, Thank you for your reply.

But the preview display has some errors.  Our usecase file is:

0640.multichhd_vcap_venc_vdis.c

and display is:

Hi Colin,

Since you are using hsync/vsync style of capture, there will be some vertical blanking region that will be captured in memory. You will have to crop this region either using VIP trimmer or in memory.

Regards,

Brijesh

Brijesh, could you help me how to do that in detail? Thanks.

Brijesh, does DM8168 captureing  support DMT Video Timing or VESA standard?  Thanks.

Yes, it supports both of these formats..

regards,

Brijesh

Hi Colin,

In hsync/vsync style of capture, vip port capture vertical and horizontal blanking area also. This size of this blanking area depends on the input resolution. There is trimmer in the vip module, using this trimmer you could trim out the blanking area and get the correct output. To enable trimming, call ioctl IOCTL_VPS_CAPT_SET_VIP_CROP_CFG with the Vps_CaptVipCropParams structure as argument. You will need to set the position and size of the cropping window. Here the position is your size of the blanking area.

Let me know if you need more information.

Regards,

Brijesh

Brijesh, Our application FPGA also output DE signal to DM8168. So FPGA output HS, VS, CLK,DE and Y/C 16 bit data bus to DM8168.

Also, I set pCaptureInstPrm->videoCaptureMode = SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC.

and I see the sample code:

vipCropPrms.channelNum = 0u;
        /* Enable VIP trimmer in discrete sync mode */
        if ((pVipCreateArgs->videoCaptureMode ==
                VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK) ||
            (pVipCreateArgs->videoCaptureMode ==
                VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC)  )
        {
            vipCropPrms.vipCropEnable = TRUE;
        }
        else
        {
            vipCropPrms.vipCropEnable = FALSE;
        }
        status = FVID2_control(
                     pInst->captureVipHandle,
                     IOCTL_VPS_CAPT_SET_VIP_CROP_CFG,
                     &vipCropPrms, NULL);
        GT_assert(GT_DEFAULT_MASK, (status == FVID2_SOK));

There is no pVipCreateArgs->videoCaptureMode ==
               SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC.

Hi Colin,

Could you also provide the parameters set in vipCropPrms.

Regards,

Brijesh

Brijesh, Our application FPGA also output DE signal to DM8168. So FPGA output HS, VS, CLK,DE and Y/C 16 bit data bus to DM8168.

Also, I set pCaptureInstPrm->videoCaptureMode = SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC.

and I see the sample code:

vipCropPrms.channelNum = 0u;
        /* Enable VIP trimmer in discrete sync mode */
        if ((pVipCreateArgs->videoCaptureMode ==
                VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK) ||
            (pVipCreateArgs->videoCaptureMode ==
                VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC)  )
        {
            vipCropPrms.vipCropEnable = TRUE;
        }
        else
        {
            vipCropPrms.vipCropEnable = FALSE;
        }
        status = FVID2_control(
                     pInst->captureVipHandle,
                     IOCTL_VPS_CAPT_SET_VIP_CROP_CFG,
                     &vipCropPrms, NULL);
        GT_assert(GT_DEFAULT_MASK, (status == FVID2_SOK));

There is no pVipCreateArgs->videoCaptureMode ==
               SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC.

Hi Colin,

You could Hsync/vsync style of capture in the if condition.

Also since DE line is also connected to the DM8168, you could even use ACTVID_VSYNC ( VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC) style of capture.

Regards,

Brijesh

Brijesh,

vipCropPrms Params is:

  vipCropPrms.channelNum = 0u;
  vipCropPrms.vipCropCfg.cropStartX = 192;
  vipCropPrms.vipCropCfg.cropStartY = 41;
  vipCropPrms.vipCropCfg.cropWidth = 1920;
  vipCropPrms.vipCropCfg.cropHeight =1080;

But there is no any display.

hi

colin he1 

last year i have use fpga to convert video to BT1120,your FPGA maybe output not correct，please check it.

maybe you use the STM292 singnal generator in your fpga?

de is not uesed,just use 16 bits lines and 1 clock line to VIN0.

and i also have some questions about mcfw.

my email:184602968@qq.com

dv

good luck

Hi Colin,

Can you please share the capture statistics? You could get the statistics by pressing 'i' while dvr-rdk is running. This will tell us exactly what frame size is getting captured. If it is not 1080p resolution, you still have to make sure it is correct by changing crop window.

Regards,

Brijesh

Also, please make sure that when you call this ioctl, capture is already not on and you are running this on DM8168 ES2.0 or later revision. This is because in earlier revision, cropping is not supported. In earlier revision, you will either have to use scalar or do cropping in memory.

regards,

Brijesh

Brijesh,

I use RDK 4.0 version, DM8168 is ES2.0.  But I think DM8168 start to capture video data by detect hs sync falling edge, not by active sync. So DM8168 also capture hs blank data. Why DM8168 not detect active sync?

Hi Colin,

There is an driver interface to change hsync/vsync/de and clock polarity. Please use this and see if it fix the issue.

Please use the structure Vps_VipPortConfig in the create time parameters to change the polarity.

Regards,

Brijesh