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C6748 Power-UP sequencing

John Smith7
Prodigy 150 points

Other Parts Discussed in Thread: TPS65070, OMAP-L132, OMAP-L138

Hi,

C6748 power-up sequence as defined in datasheet (section 5.3.1) states that power-up sequence should be:

RTC_CVDD --> Core 1.2V --> static 1.2V --> all static 1.8V -->  All 3.3V.

Now, Application report for TPS65070 (SLVA371B) shows that the sequence is dependent on LVCMOS operating voltage.

For DVDD3318ABC @1.8V:  RTC_CVDD --> Core 1.2V --> static 1.2V --> DVDD@1.8V --> all static 1.8V -->  All 3.3V.

For DVDD3318ABC @3.3V:  RTC_CVDD --> Core 1.2V --> static 1.2V --> all static 1.8V -->  DVDD@3.3V --> All 3.3V 

The datasheet does not mandate DVDD3318 supplies to be powered before static rails, neither does the ref. manual. Is this an oversight in the datasheet?

The problem I have is that I can't use TPS65070 because it does not offer external sync clock option. My application requires all PSUs to be locked to a master clock source. 


Thanks,

J

Powering OMAP-L132-L138, C6748 using TPS65070.pdf
  • 0
    TI__Expert 4760 points

    Hi John Smith,

    The power app note clearly defines the sequence order in Table.2 that matches the datasheet conditions

     

    Table 2. OMAP-L132/L138 Power Groups

     

    Order

    Group

    Voltage

    1

    RTC12

    1.2 V

    2

    STATIC12

    1.2 V

    3

    STATIC18

    1.8 V

    4

    STATIC33

    3.3 V

     

    More over There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V supplies by more than 2 volts.

    Regards

    Antony

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  • 0 in reply to Antony Samsunil
    Prodigy 150 points

    Hi Antony,

    Thanks for your reply.


    In such case can you please explain the reason for the added delay between static 1.8V and DVDD3318 running at 1.8V (T2 in attached picture)?

    Regards,

    J

  • 0 in reply to John Smith7
    TI__Expert 4760 points

    Hi John,

    The application note says the output of the LDO1 to the OMAP-L138/C6748 delayed by an external circuit consisting of T1, T2, R3 and R4 to meet the correct power-up sequence requirements.

    Bu the in the power requirement Table 1 they didn’t mentioned anything about Time delay.

    So, with respect to datasheet, if 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails (VDDA33_USB0/1).Absolutely there is no need of time delay in between them.

    Basically we need the 1.2V ramped up to nominal level before you start ramping up the 1.8V then followed by 3.3V any realistic delay should be ok, but I don’t see any requirement for delay in between static 1.8V and LVCMOS 1.8V supply.

    Please check the similar kind of discussion

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/108307/382749.aspx#382749

    Please refer the other application note too

    http://www.ti.com/lit/an/slva342b/slva342b.pdf

    http://www.ti.com/lit/an/slva340a/slva340a.pdf

    http://www.ti.com/lit/an/slva339c/slva339c.pdf

    Regards

    Antony

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  • 0 in reply to Antony Samsunil
    Prodigy 150 points

    Thanks for clarifying this.

    Regards,

    J