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EVM6657LS/SPI boot: does DSP restructure the .bin read from NOR flash

GregorS
Intellectual 500 points

hi,

I managed to write a simple "hello world" program on the NOR Flash on my EVM6657LS and boot successfully afterwards in SPI mode. As I want to replace the NOR Flash by a FPGA FIFO (to boot directly from FPGA as SPI Slave) on my own board, I would like to know if the DSP is following some kind of protocol while reading the .bin from NOR Flash (e.g. hopping among several addresses). As I cannot hop in my FIFO in future, I need to know how to arrange the boot file. 

Before analyzing the bit stream between NOR Flash and DSP via Scope, I want to ask here.

Thanks+Regards, Gregor

  • 0
    TI__Guru** 116870 points

    Gregor,

    The Boot ROM doesn`t typically jump addresses but there are certain conditions under which this may not be true.

    • Are you loading your own parameter table which chnages the offset from which your SPI boot image needs to be read?
    • Are you planning to use two stage boot or a single stage boot.?

    If you aren`t doing any of the above then the RBL will tend to read sequentially from the SPI port.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 500 points

    HI Rahul,

    thanks for reply! You are doing a really good job. Development with TI products would be much more complicated without having this forum.

    Difficult questions to answer:

    2) I plan to choose SPI as boot mode, boot some small program from FPGA-FIFO (now on EVM as NOR Flash) which basically initializes PLL, DDR3 and PCIe-Interface (if not done yet) and starts requesting via PCIe more data from FPGA (is PCIe EP). You could see it as a kind of IBL on NOR Flash, but as the IBL is always booted via I²C, I would interprete it as "single stage boot" and afterwards some customer code, which is to request some more program code and execute it afterwards.

    1) I do not know. Where can I look for that? I am using a .bat-file by "George" (maybe you know the big threads about SPI booting in this forum). I added the file package, I am using for converting my .out file to a "SPI bootable" .bin. Just paste some .out file in the folder and run "mySpiBoot.bat". Also another way to express my question in the first thread: Do you know, if this converting process is customized for the specific NOR Flash on the EVM or does it just depend on SPI-mode?

    6332.George_Boot_5040_TI.zip

    Thanks + Regards, Gregor

  • 0 in reply to GregorS
    TI__Guru** 116870 points

    Hi Gregor,

    I am not 100% clear regarding your setup where you have an initial boot image to do the PLL settings, DDR setup and PCIe setup. and then load some customer code. PLL configuration and DDR settings can be done on C6657 using the RBL with the help of parameter table and DDR3 configuration table. Are you saying you plan to do this using your own code rather than the RBL. PCIe setup will need to be done using code as there is no provision to setup PCIe when you are booting from SPI. 

    From what I see you are using the base address of the SPI NOR to boot the initial image.This should work with FPGA-FIFO setup as the RBL implements a sequential read when it knows the base address from which it needs to read the boot table. The RBL code for C6657 is released here:

    http://processors.wiki.ti.com/index.php/Keystone_Device_Architecture

    Can you help us understand how the custom code is loaded after the device initialization image is loaded. If this is done by re-entring boot and starting a read from a different SPI offset location the RBL will jmp to reading from that address.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 500 points

    HI Rahul,

    as I am very new to DSP topic in general, it is quite probable that my suggested solution for the boot process is not the most efficient way.

    Our general aim is to get some data/user code into DSP/DDR3 and to allow communication with an FPGA (necessarily PCIe EP) via PCIe. As far as I know booting the DSP via PCIe is just possible if the DSP is EP. And without rebooting it is not possible to change its role. Thats why we cannot use PICe bootmode in our configuration.

    If I understand you right, the DSP is executing the initialization phase of the RBL in no-boot mode? But I do not know how I can tell the RBL to evoke a communication via PCIe to load user code. Thats why I used SPI bootmode to store some code snippet in the NOR Flash to tell the DSP to evoke a PCIe communication. This code is at the moment almost the same like the PCIe example (link training). But I thought that I could extend it to some real communication, where user code is loaded to the DSP and executed afterwards.

    I hope that I could express my situation more precisely. Its nothing special, I guess. Just that I cannot boot via PCIe because DSP has to be RC. I checked the SPRUGY5C and RBL source code again. But for me I cannot extract any new information which would help me to find any other solution.

    Thanks for help + Regards,

    Gregor