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Could A8 host share DSP image processing loading

Joey Lin
Intellectual 670 points

Hi, there:

Currently we have Video-M3 received capture images, passing to DSP via shared buffer for processing.  Video-M3 deinterlace and display video again via shared buffer after DSP has done its jobs.  DSP and Video-M3 communicate thru MessageQ.  

Due to the fact that the DSP loading  in our application is so high that it has caused frame rate dropping.  To diverse the image processing loading, we wonder is there any way possible that we may take advantage of A8 to share DSP loading so that M3 could pass images to A8 as well as DSP and DSP may also received images from A8 for post-processing? Is there an example for reference?

Thanks in advance for your expertise,

My platform info: TMS320DM8148 (Vision-Mid) 

600-MHz ARM® Cortex™-A8 RISC MPU

500-MHz C674x™ VLIW DSP

200-MHz M3-ISS/M3-HDVPSS 

Thanks in advance,

Joey from Altek

  • 0
    TI__Expert 3265 points

    Hi Joey,

    It is possible to distribute processing to include the A8 host.

    Can you tell us if you are currently using any 'framework' (e.g. OMX, Codec Engine, GStreamer, etc.,) on the DSP and Video-M3 cores? In your current application is the A8 communicating with the other cores, and if so what underlying mechanism/framework is being used? Also the Host O/S?

    Best regards,

    Murat

  • 0 in reply to raormanrat
    Intellectual 670 points

    Hi, Murat:

    Thank you for your responding. In our application, we have only used TI library, such as VLIB, or imglib for image processing in DSP that is captured by camera, formated, resized by M3-video and shared via shared frame buffer between cores.  Therefore, I don't think we have used a framework.  A8 is acting as host. In fact, we have always followed TI 8148 AV-BIOS demo structure, the A8 controls the IPC communication, please see page 17 of the attached sdk user guide (Block Diagram of the System (Cortex-A8 Master)) for details.  

    6180.av_bios_sdk_userguide.pdf   

    So far, I am struggling to make EDMA3 working in A8. I've had the DMA working in DSP, so I moved the DMA folder to A8 and called DAT_EDMA3LLD_init() in a8 task thread. It failed with returning error, "[CortexA8] edma3init() FAILED, error code: -128" (EDMA3_DRV_E_RM_CLOSE_FAIL), or -139(EDMA3_DRV_E_INVALID_PARAM) if I change edma3Id from 0 to 1.

    Any idea for how to fix this is highly appreciated,

    have a good one,

    Joey from Altek

  • 0 in reply to Joey Lin
    Intellectual 670 points

    Hi, Murat:

    Just to inform you that the EDMA3 issue has been resolved. The EDMA3 init was already been done in early stage of the main function by calling a different init API that also contains edma3init() in the common directory of the AV-BIOS sdk. And I was not aware of that. That was why the -128  (EDMA3_DRV_E_RM_CLOSE_FAIL) is returned because the dma object was previously open.

    Regards,

    Joey from Altek

     

  • 0 in reply to raormanrat
    Intellectual 670 points

    Hi, Murat:

    When processing images on A8, I may need to use on-chip memory (L2) to speed up the performance. 

    My question is that could A8 512K L2 be used as a SDRAM for DMA+PingPong Processing just like in dsp?

    Best regards,

    Joey from Altek

  • 0 in reply to Joey Lin
    TI__Genius 12025 points

    Joey,

    I don't think you can access the ARM L2 Cache as internal SRAM. And I think the ARM local RAM 64KB is only accessible from the ARM, not the DSP.

    You might try asking this question in a hardware forum. Try the following one:

    DM814x and AM387x Processors Forum
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716.aspx

    ~Ramsey

  • 0 in reply to Ramsey
    Guru 10685 points

    I would try getting the source code for the imagelib and optimising it for your particular DSP. The imagelib was probably built to only support the simplest of DSPs when the more recent ones have plenty of L1 and L2 SRAM to help speed things up.