The PLL0 configuration in the C6748 gel script(s) have the following step:
/* Enable the PLL output*/
PLL0_PLLCTL &= ~(0x00000010);
SPRUH79A, Table 7-8 page 143 states about PLLCTL bit 4 (default value is 1): "Reserved. Write the default value when modifying this register."
What is the gel script doing?
-- bradley
