External linking memory allocation

selvaraj v

I confused with memory allocation that needs to be done with respect to external lnk ram, confusing exiting with what is the entry size for each descriptor. Assuming i allocate 512 k external lnk ram , what is the size that needs to be allocated 512k*4 or 512k *8 ?

The following statement are the cause of the confusion

1) CPPI/QMSS LLD
5.3 QMSS DESIGN DETAILS
The Queue Manager provides high-performance descriptor management. A total of 512 K
descriptors can be managed by the queue manager and these descriptors can be pooled into up to
8 K queues. To track the location of the descriptors in the queues, the queue manager uses
4x512 KB of memory. Up to 4x16 KB of this memory can be in the Linking RAM that is
embedded inside the QMSS and the remaining memory can be located elsewhere inside or
outside the device.

2) CPPI/QMSS LLD
11.2 Linking RAM
o 16K descriptors can be tracked using the internal linking RAM.
o Use External linking RAM for additional descriptors.
o Each entry MUST be 64 bit wide.
o Sum of internal and external memory MUST be equal to or greater than maximum
number of descriptors used in the system.

3 ) KeyStone Architecture Multicore Navigator User Guide
6.2.1 QMSS Initialization
An external Linking RAM needs to be configured with one 64-bit word for each
descriptor in the memory regions that use the external Linking RAM. The internal
Linking RAM does not require a buffer to be allocated for it

4) Multicore Navigator:Queue Manager Subsystem (QMSS)
Step 2: Linking RAM Setup
The Linking Ram is configured in one or two pieces, though it is used (by QM) as a single unit.
Requires one n-bit word per descriptor index, where n =
   40 bits for the internal linking RAM
   Benefit: speed (much faster than any other memory)

   64 bits for an external linking RAM
   Benefit: size (up to 512K entries)

thanks

selvaraj

over 12 years ago

0 Pubesh over 12 years ago

TI__Mastermind 20790 points

Selvaraj,

Please mention the details of which TI device using by you.
The Low Level Driver(LLD) will always take care the size in descriptor entries.
The only time the *4 comes into play is if you want to "malloc" the memory for external linking RAM.
You can refer this thread got verified and also similar your question.
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/193739/694609.aspx#694609
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/266450/934364.aspx#934364

0 selvaraj v over 12 years ago in reply to Pubesh

Prodigy 90 points

The device i am using is 6678.

The link you have provided does not answer my question

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/193739/694609.aspx#694609
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/266450/934364.aspx#934364

I understand the difference between external and internal lnk ram , i have a working code base with external link ram. My contention has been memory allocation for external lnk ram , to be safe i have allocated for 256k buffer 256*1024*8 ( 2m memory ) and code is working. I will try to explain what i have implement.

I have created external link ram and code is as below

#define MAX_NUM_DESC_SUPPORTED     (256 * 1024)
#define MAX_NUM_DESC_IN_INTLNKRAM (16 * 1024)

Qmss_InitCfg            qmssInitConfig;

qmss_extlnkram = (uint8_t *) Memory_alloc(HEAP_QMSS_EXTLINKRAM, sizeof(uint64_t) *
               (MAX_NUM_DESC_SUPPORTED - MAX_NUM_DESC_IN_INTLNKRAM), CACHE_L2_LINESIZE);

qmssInitConfig.linkingRAM0Base =   0;
qmssInitConfig.linkingRAM0Size =   0;
qmssInitConfig.linkingRAM1Base =   (uint32_t) qmss_extlnkram;
qmssInitConfig.maxDescNum       =   totalNofDesc;

qmssInitConfig.pdspFirmware[0].pdspId   = Qmss_PdspId_PDSP1;
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;
qmssInitConfig.pdspFirmware[0].size     = sizeof (acc48_le);

result = Qmss_init (&qmssInitConfig, &qmssGblCfgParams[0]);

My concern is , as mentioned in previous mail , size of individual entry in link ram . If the size is 4 bytes then i have to allocate 4*256*1024 which 1 mb and if the entry is 8 bytes 8*1024*256 which is 2mb.

I have mentioned two statement in LLD which seems to be contradictory , re pasting it

1) CPPI_QMSS_LLD_SDS.pdf
5.3 QMSS DESIGN DETAILS
The Queue Manager provides high-performance descriptor management. A total of 512 K
descriptors can be managed by the queue manager and these descriptors can be pooled into up to
8 K queues. To track the location of the descriptors in the queues, the queue manager uses
4x512 KB of memory. Up to 4x16 KB of this memory can be in the Linking RAM that is
embedded inside the QMSS and the remaining memory can be located elsewhere inside or
outside the device.

2) CPPI_QMSS_LLD_SDS.pdf
11.2 Linking RAM
o 16K descriptors can be tracked using the internal linking RAM.
o Use External linking RAM for additional descriptors.
o Each entry MUST be 64 bit wide.
o Sum of internal and external memory MUST be equal to or greater than maximum
number of descriptors used in the system.

question is how must memory should be allocated to hold 256k descriptor ?

0 Xiaohui Li over 12 years ago in reply to selvaraj v

TI__Intellectual 1870 points

Hi,

The Linking RAM unit size should be 64bits.

Xiaohui

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External linking memory allocation