HOW to config GPMC connected with FPGA?

jiabo yu

Other Parts Discussed in Thread: AM3352

hi:

all,i have designed GPMC moduled connected with FPGA.but i have some problems about configuration wtih GPMC_CONFIG1---GPMC_CONFIG7,and i designed as follow:

1)FPGA used for 16bit write and read;

2) addr pins :GPMC_A11 --- GPMC_A1(highest 11 bit),GPMC_AD15 --- GPMC_AD0(lowest 16bit);

3) data pins:GPMC_AD15 --- GPMC_AD0;in other words GPMC is in Address and data multiplexed attached device.

4) FPGA is connected through GPMC_CS1;

5) my paltfrom is AM3352,used startware kit. not linux system.

I want to write/read with in sync mode.how should i config GPMC_CONFIG1---GPMC_CONFIG7?

I tryed as follow:

1) pins mux cpnfig:

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(1) ) =
              (0 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2) ) =
              (0 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(3) ) =
              (0 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4) ) =
              (0 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5) ) =
              (0 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(6) ) =
              (0 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7) ) =
              (0 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(8) ) =
              (0 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(9) ) =
              (0 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10) ) =
              (0 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_SLEWCTRL_SHIFT);

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11) ) =
              (0 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE_SHIFT)     |
              (0 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN_SHIFT)     |
              (1 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL) |
              (0 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE_SHIFT) |
              (0 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_SLEWCTRL_SHIFT);

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0) ) = 0x30;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4) ) = 0x30;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6) ) = 0x30;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7) ) = 0x30;

//GPMC_AD8~GPMC_AD15
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(8) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(9) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(10) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(11) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(12) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(13) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(14) ) = 0x30;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(15) ) = 0x30;

        // CONF_GPMC_CS1N for FPGA Chip-Select
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(1) ) =
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE_SHIFT)     |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN_SHIFT)     |
     (1 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL_SHIFT) |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE_SHIFT) |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL_SHIFT);

        // CONF_GPMC_CS1N for FPGA Chip-Select
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(2) ) =
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE_SHIFT)     |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN_SHIFT)     |
     (1 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL_SHIFT) |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE_SHIFT) |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL_SHIFT);

        // CONF_GPMC_CS1N for FPGA Chip-Select
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3) ) =
     (7 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE_SHIFT)     |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN_SHIFT)     |
     (1 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL_SHIFT) |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE_SHIFT) |
     (0 << CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL_SHIFT);

    // BE1n, BE0n, CS2n, OEn, WEn
// CONF_GPMC_WEN
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN ) =
     (0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT)     |
     (0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT)     |
     (1 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
     (0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT) |
     (0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_SLEWCTRL_SHIFT);

// CONF_GPMC_OEN_REN
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN ) =
     (0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT)     |
     (0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT)     |
     (1 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) |
     (0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT) |
     (0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_SLEWCTRL_SHIFT);

// CONF_GPMC_BE0N_CLE
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE0N_CLE ) =
   (0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE)   |
   (0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT)    |
   (1 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT)|
   (0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT) |
   (0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_SLEWCTRL_SHIFT);

// CONF_GPMC_BE1N
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE1N ) =
   (0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE_SHIFT) |
   (0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN_SHIFT)    |
   (1 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL_SHIFT)|
   (0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE_SHIFT) |
   (0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_SLEWCTRL_SHIFT);

// CONF_GPMC_CLK
   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CLK ) =
   (0 << CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_MMODE_SHIFT)    |
   (1 << CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUDEN_SHIFT)    |
   (1 << CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUTYPESEL_SHIFT)|
   (1 << CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RXACTIVE_SHIFT) |
   (0 << CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_SLEWCTRL_SHIFT);

2) GPMC_CONFIG1---GPMC_CONFIG7:

        HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG7( FPGA_SRAM_CHIP_SELECT ) )= 0;

        //GPMC_CONFIG1_i
        HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG1(FPGA_SRAM_CHIP_SELECT) ) = 0x28001200;

//GPMC_CONFIG2_i
HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG2(FPGA_SRAM_CHIP_SELECT) ) = 0x00060700;

//GPMC_CONFIG3_i Chip-select signal timing parameter configuration
HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG3(FPGA_SRAM_CHIP_SELECT) )= 0x11010100;

//GPMC_CONFIG4_i WE# and OE# signal timing parameter configuration
HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG4(FPGA_SRAM_CHIP_SELECT) )= 0x0602e722;

//GPMC_CONFIG5_i RdAccess Time and Cycle Time parameter configuration
HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG5(FPGA_SRAM_CHIP_SELECT) )= 0x01060607;

//GPMC_CONFIG6_i WrAccess, WrDataOnADmuxBus, Cycle2Cycle, and BusTurnAround parameter configuration
HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG6(FPGA_SRAM_CHIP_SELECT) )= 0x030301c1;

//GPMC_CONFIG7_i Chip-Selectaddress mapping configuration

HWREG(GPMC_CONFIG_REGS + GPMC_CONFIG7( FPGA_SRAM_CHIP_SELECT ) )=
   (0x0 << GPMC_CONFIG7_1_BASEADDRESS_SHIFT) |
   (1  << GPMC_CONFIG7_1_CSVALID_SHIFT)|
   (0x00 << GPMC_CONFIG7_1_MASKADDRESS_SHIFT);

But GPMC_CLK is not output!

Anyone could give some help? BASEADDR IS WRONG ? or have some pin mux wrong?

Thanks.

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Two comments:

1. GPMC_CLK is output only if synchronous access is configured.

2. The GPMC_CLK pinmux must have receiver enabled, otherwise read operations will not function.

0 jiabo yu over 11 years ago in reply to Biser Gatchev-XID

Intellectual 370 points

Thanks fot your reply!

I have configed the regs CONFIG1 to 0X28001200;

READ and WRITE mode is synchronous;

and the pin of GPMC_CLK is confged to (1 << 5) | (1 << 4) | (1 << 3); RX is active too;

why the GPMC_CLK cannot be output?

The cs0 baseaddr is 0x08000000 for NAND;size is 256M

The cs1 baseaddr is 0x18000000 for FPGA;size is 256M;

AND I write data to FPGA as follow:

for (i = (1 << 20);(FPGA_SRAM_BASEADDR + i) < 0x20000000;i+=(1 << 20))
{
HWREG((FPGA_SRAM_BASEADDR + i)) = 0x55aa;
}

That 's to say already acessing the all gpmc SIZE (0X0 ~ 0X1FFFFFFF);

Anything wrong or make some mistake?

Thanks;

0 Biser Gatchev-XID over 11 years ago in reply to jiabo yu

TI__Guru**** 393215 points

jiabo yu said:
for (i = (1 << 20);(FPGA_SRAM_BASEADDR + i) < 0x20000000;i+=(1 << 20))

This seems strange to me. Also, what are your GPMC_CONFIG7 values?

0 jiabo yu over 11 years ago in reply to Biser Gatchev-XID

Intellectual 370 points

The for code:

for (i = (1 << 20);(FPGA_SRAM_BASEADDR + i) < 0x20000000;i+=(1 << 20))
{
HWREG((FPGA_SRAM_BASEADDR + i)) = 0x55aa;
}

is to serach the proper baseaddr and those are testing code;

but GPMC_CLK pin is not outpt;

the GPMC_CONFIG7 is configed to (0x18) | (1 << 6) | 0;

The cs0 baseaddr is 0x08000000 for NAND;size is 256M

The cs1 baseaddr is 0x18000000 for FPGA;size is 256M;

Thanks!

0 Biser Gatchev-XID over 11 years ago in reply to jiabo yu

TI__Guru**** 393215 points

CONFIG7 is fine, I am not convinced your for() conditions are correct.

0 jiabo yu over 11 years ago in reply to Biser Gatchev-XID

Intellectual 370 points

and how should i test writing and read to FPGA?

the pin GPMC_CLK is not output?why?

the pinmux and config1 ~ config7 are configered.

0 Biser Gatchev-XID over 11 years ago in reply to jiabo yu

TI__Guru**** 393215 points

One more thing - GPMC_CLK is not output continuously. It is output only during read/write accesses to the GPMC.

0 jiabo yu over 11 years ago in reply to Biser Gatchev-XID

Intellectual 370 points

there is a problem i want to confirm that how to confirm the souce of GPMC_CLK is enable?

and the for testing code is continuous running.

how should i solve the problem? and could you give some idea about to test writging and reading from FPGA?

Thanks.

0 Biser Gatchev-XID over 11 years ago in reply to jiabo yu

TI__Guru**** 393215 points

What I can suggest is that you draw the tining diagram you need for accessing the FPGA. Use the figures available in the AM335X TRM Rev. J, section 7 to understand the different timings that can be selected in the GPMC_CONFIG registers and check your settings. I still don't like this for () cycle that you posted, in it parameter i is incremented by a step of 1<<20.

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HOW to config GPMC connected with FPGA?