C6657 SRIO 1x/2x/4x configuration

YUCHAO WANG

Hi TI engineer:

We have an application to connect C6657 to FPGA in 2 1xport. Now it's not successful,for investigating the problem,can you tell me:

1.if I config port 0 1 2 3 to path mode0, then I divide SRIO to four 1x port,isn't it?

2.If I config port 0 1 to path mode0,then I divide SRIO to two 1x port, and what I do to port 2 3 will be unmeanningful,isn't it?

3.when srio works in 2 or 4 1xport, each port can connect to target, they don't influence on each other at all, isn't it?

Look forward to reply, thank you very much!

over 11 years ago

0 Ganapathi Dhandapani95 over 11 years ago

TI__Mastermind 28085 points

Hi YUCHAO WANG,

Please refer below link for detailed SRIO port configuration information.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/127613/477186.aspx#477186

Thanks.

0 YUCHAO WANG over 11 years ago in reply to Ganapathi Dhandapani95

Expert 1265 points

Hi Quote

When I click on the link it doesn't let me in.The information showing on computer have been attached to this reply.

Still I want to know that if 2 1x port linked to different devices,is it allowed?Thank you very much.

0 Jack S over 11 years ago in reply to Ganapathi Dhandapani95

Intellectual 850 points

the link is not accessable now

0 Ganapathi Dhandapani95 over 11 years ago in reply to Jack S

TI__Mastermind 28085 points

Hi YUCHAO WANG,

I copied the above link message below

Path mode = 0, sets up the peripheral for 4 ports, each 1X wide. Path mode = 4, sets the peripheral for 1 port 4X wide. See the below figure (C66x devices support Configuration 4)

The link rate is setup completely independent of the port width above and uses the SerDes registers. As an example, if Path mode = 4, and the SerDes are setup for 5Gbps operation, you would have a single port giving you 20Gbps operation (max 16Gbps of theoretical bandwidth).

Refer section "2.3.1.4 SerDes Configuration Example" in KeyStone Architecture Serial Rapid IO (SRIO) User Guide (sprugw1).

http://www.ti.com/lit/sprugw1

Thanks,

0 YUCHAO WANG over 11 years ago in reply to Ganapathi Dhandapani95

Expert 1265 points

Hello

Thank you for replying.I still have one last question.Since each port's mode could be configure independently(we can certify it in the code),then I'm curious about:

What will happen if I configure port0 to mode0 with port1 to mode1?They are contradict at all,isn't it?

If I set port0 to mode4, does port 1-3 unexist?If I do some operation on port1-3, is it influential on the srio?

Regards, Yuchao.

0 Ganapathi Dhandapani95 over 11 years ago in reply to YUCHAO WANG

TI__Mastermind 28085 points

Hi Yuchao,

Lane configuration is set by PATH_MODE, CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0); So this is being set to mode 0, which is (4) 1x ports.

CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 4); So this is being set to mode 4, which is (1) 4x port.

Refer section "1.2 RapidIO Feature Support in SRIO" in sprugw1.

4X Serial RapidIO with auto-negotiation to
– 1X port, optional operation for (4) 1X ports
– 2X port, optional operation for (2) 2X ports
– 2X port and 1X port operation, optional operation for (1) 2X port and (2) 1X
ports
– 4x port, operation for (1) 4x port

Thanks,

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C6657 SRIO 1x/2x/4x configuration