sfh_OMAP-L138 - problem detecting the board

Gaby Levy

Intellectual 410 points

Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Hello

This is my configuration:

Board: EVMC6748 (I am using the TMS320C6748 DSP).

I am connected using the ethernet port to my router.

ccs: 5.4.0.00091

bios: 6_35_01_29

pspdrivers: 01_30_01

nsp: nsp_1_10_02_09

ndk: ndk_2_22_03_20

xdctools: 3_25_00_48

xgconf

I prepared BIN file using AIS according to the described in " http://software-dl.ti.com/trainingTTO/trainingTTO_public_sw/bios/BIOS_14b_Flash.pdf"

I am working based on the description in http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138

I am trying to run the sfh tool...

sfh_OMAP-L138 -targetType C6748_LCDK -erase -p COM2 -v

I am getting the following:

[TYPE] Global erase

[TARGET] C6748_LCDK

[DEVICE] SPI_MEM

[SPI Block] 0

Attempting to connect to device COM2...

Press any key to end this program at any time.

(AIS Parse): Read magic word 0x41504954

(AIS Parse): Waiting for BOOTME... (power on or reset target now)

---

Now, I am getting the same also if I am not connecting the board to power... I mean only connecting the USB to my computer and I am getting the same, so I guess for some kind of reason we cannot speak with the device.

I tried to change the targetType to OMAPL138, OMAPL138_LCDK and C6748, it did not help.

The Dip switch configuration is all OFF except 7 and 8, ON

Any ideas?

Thanks in advance,

GBL

over 11 years ago

0 Gaby Levy over 11 years ago

Intellectual 410 points

Well eventually I managed to program the flash this way, but I still have a problem - it seems the unit is restarting again and again.

This is what I did:

1) DS status: 1=OFF, 2=ON, 3=OFF, 4=ON (According to document "L138/C6748 Development Kit (LCDK) - Texas Instruments Wiki")

2) AIS I prepared telling the flash is NAND

3) I used sfh utility: C:\BIOSv4\OMAP-L138_FlashAndBootUtils_2_40\OMAP-L138\GNU>sfh_OMAP-L138 -flash_noubl c:\BIOSv4\Labs\SensorPrj_NAND.bin -flashType NAND -targetType C6748_LCDK -p

So, the tool says I managed to program the flash

Then I put all DS in OFF state, but it seems the unit is restarting again and again.

It can be some mapping issue? How do I test it? Is it possible to debug?

Thanks in advance,

GBL

0 Titusrathinaraj Stalin over 11 years ago in reply to Gaby Levy

TI__Guru** 116100 points

Hi Gaby,

Can you please attach your complete output logs ?

Are you hang at "Waiting SFT..." or "Waiting for "BOOTME" ?

Is this your custom or EVM board ?

Board: EVMC6748 (I am using the TMS320C6748 DSP).

I assume that this is C6748EVM board.

sfh_OMAP-L138 -targetType C6748_LCDK -erase -p COM2 -v

3) I used sfh utility: C:\BIOSv4\OMAP-L138_FlashAndBootUtils_2_40\OMAP-L138\GNU>sfh_OMAP-L138 -flash_noubl c:\BIOSv4\Labs\SensorPrj_NAND.bin -flashType NAND -targetType C6748_LCDK -p

Are you getting "BOOTME" text in serial port (COM2) ?

Ensure that you have closed serial port before running the serial flasher utility.

Then I put all DS in OFF state, but it seems the unit is restarting again and again.

Set DIP switch settings to "serial" option.

http://processors.wiki.ti.com/index.php/C6748_StarterWare_Booting_And_Flashing

0 Gaby Levy over 11 years ago in reply to Gaby Levy

Intellectual 410 points

Hi...

Attached "programming.txt" shows that the programming was ok...

But as I wrote something still not woking as my application does not start...

Fullscreen 4403.programming.txt Download

C:\BIOSv4\OMAP-L138_FlashAndBootUtils_2_40\OMAP-L138\GNU>sfh_OMAP-L138 -flash_n
ubl c:\BIOSv4\Labs\SensorPrj_NAND.bin -flashType NAND -targetType C6748_LCDK -p
COM2 -v
-----------------------------------------------------
   TI Serial Flasher Host Program for OMAP-L138
   (C) 2012, Texas Instruments, Inc.
   Ver. 1.67
-----------------------------------------------------


      [TYPE] Single boot image
[BOOT IMAGE] c:\BIOSv4\Labs\SensorPrj_NAND.bin
    [TARGET] C6748_LCDK
    [DEVICE] NAND
    [NAND Block] 1

Attempting to connect to device COM2...
Press any key to end this program at any time.

(AIS Parse): Read magic word 0x41504954.
(AIS Parse): Waiting for BOOTME... (power on or reset target now)
(AIS Parse): BOOTME received!
(AIS Parse): Performing Start-Word Sync...
(AIS Parse): Performing Ping Opcode Sync...
(AIS Parse): Processing command 0: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 19808-Byte section to address 0x11800000.
(AIS Parse): Processing command 1: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 1364-Byte section to address 0x11804D60.
(AIS Parse): Processing command 2: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 20-Byte section to address 0x118052F0.
(AIS Parse): Processing command 3: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 16-Byte section to address 0x11805304.
(AIS Parse): Processing command 4: 0x58535906.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Performing jump and close...
(AIS Parse): AIS complete. Jump to address 0x11804620.
(AIS Parse): Waiting for DONE...
(AIS Parse): Boot completed successfully.

Waiting for SFT on the OMAP-L138...
        Target: BOOTUBL
        Target:    DONE

Flashing application c:\BIOSv4\Labs\SensorPrj_NAND.bin (410932 bytes)

        Target: SENDIMG
        Target:   BEGIN
 100% [ ������������������������������������������������������������ ]
                  Image data transmitted over UART.

        Target:    DONE
   0% [ ------------------------------------------------------------ ]
                Programming application into flash...

        Target: Writing to block 0x00000001, address  0x00020000
        Target: CurrBlockNum =0x00000001
        Target: Writing image data to Block 0x00000001, Page 0x00000000
        Target: Writing image data to Block 0x00000001, Page 0x00000001
        Target: Writing image data to Block 0x00000001, Page 0x00000002
        Target: Writing image data to Block 0x00000001, Page 0x00000003
        Target: Writing image data to Block 0x00000001, Page 0x00000004
        Target: Writing image data to Block 0x00000001, Page 0x00000005
        Target: Writing image data to Block 0x00000001, Page 0x00000006
        Target: Writing image data to Block 0x00000001, Page 0x00000007
        Target: Writing image data to Block 0x00000001, Page 0x00000008
        Target: Writing image data to Block 0x00000001, Page 0x00000009
        Target: Writing image data to Block 0x00000001, Page 0x0000000A
        Target: Writing image data to Block 0x00000001, Page 0x0000000B
        Target: Writing image data to Block 0x00000001, Page 0x0000000C
        Target: Writing image data to Block 0x00000001, Page 0x0000000D
        Target: Writing image data to Block 0x00000001, Page 0x0000000E
        Target: Writing image data to Block 0x00000001, Page 0x0000000F
        Target: Writing image data to Block 0x00000001, Page 0x00000010
        Target: Writing image data to Block 0x00000001, Page 0x00000011
        Target: Writing image data to Block 0x00000001, Page 0x00000012
        Target: Writing image data to Block 0x00000001, Page 0x00000013
        Target: Writing image data to Block 0x00000001, Page 0x00000014
        Target: Writing image data to Block 0x00000001, Page 0x00000015
        Target: Writing image data to Block 0x00000001, Page 0x00000016
        Target: Writing image data to Block 0x00000001, Page 0x00000017
        Target: Writing image data to Block 0x00000001, Page 0x00000018
        Target: Writing image data to Block 0x00000001, Page 0x00000019
        Target: Writing image data to Block 0x00000001, Page 0x0000001A
        Target: Writing image data to Block 0x00000001, Page 0x0000001B
        Target: Writing image data to Block 0x00000001, Page 0x0000001C
        Target: Writing image data to Block 0x00000001, Page 0x0000001D
        Target: Writing image data to Block 0x00000001, Page 0x0000001E
        Target: Writing image data to Block 0x00000001, Page 0x0000001F
        Target: Writing image data to Block 0x00000001, Page 0x00000020
        Target: Writing image data to Block 0x00000001, Page 0x00000021
        Target: Writing image data to Block 0x00000001, Page 0x00000022
        Target: Writing image data to Block 0x00000001, Page 0x00000023
        Target: Writing image data to Block 0x00000001, Page 0x00000024
        Target: Writing image data to Block 0x00000001, Page 0x00000025
        Target: Writing image data to Block 0x00000001, Page 0x00000026
        Target: Writing image data to Block 0x00000001, Page 0x00000027
        Target: Writing image data to Block 0x00000001, Page 0x00000028
        Target: Writing image data to Block 0x00000001, Page 0x00000029
        Target: Writing image data to Block 0x00000001, Page 0x0000002A
        Target: Writing image data to Block 0x00000001, Page 0x0000002B
        Target: Writing image data to Block 0x00000001, Page 0x0000002C
        Target: Writing image data to Block 0x00000001, Page 0x0000002D
        Target: Writing image data to Block 0x00000001, Page 0x0000002E
        Target: Writing image data to Block 0x00000001, Page 0x0000002F
        Target: Writing image data to Block 0x00000001, Page 0x00000030
        Target: Writing image data to Block 0x00000001, Page 0x00000031
        Target: Writing image data to Block 0x00000001, Page 0x00000032
        Target: Writing image data to Block 0x00000001, Page 0x00000033
        Target: Writing image data to Block 0x00000001, Page 0x00000034
        Target: Writing image data to Block 0x00000001, Page 0x00000035
        Target: Writing image data to Block 0x00000001, Page 0x00000036
        Target: Writing image data to Block 0x00000001, Page 0x00000037
        Target: Writing image data to Block 0x00000001, Page 0x00000038
        Target: Writing image data to Block 0x00000001, Page 0x00000039
        Target: Writing image data to Block 0x00000001, Page 0x0000003A
        Target: Writing image data to Block 0x00000001, Page 0x0000003B
        Target: Writing image data to Block 0x00000001, Page 0x0000003C
        Target: Writing image data to Block 0x00000001, Page 0x0000003D
        Target: Writing image data to Block 0x00000001, Page 0x0000003E
        Target: Writing image data to Block 0x00000001, Page 0x0000003F
        Target: Writing image data to Block 0x00000002, Page 0x00000000
        Target: Writing image data to Block 0x00000002, Page 0x00000001
        Target: Writing image data to Block 0x00000002, Page 0x00000002
        Target: Writing image data to Block 0x00000002, Page 0x00000003
        Target: Writing image data to Block 0x00000002, Page 0x00000004
        Target: Writing image data to Block 0x00000002, Page 0x00000005
        Target: Writing image data to Block 0x00000002, Page 0x00000006
        Target: Writing image data to Block 0x00000002, Page 0x00000007
        Target: Writing image data to Block 0x00000002, Page 0x00000008
        Target: Writing image data to Block 0x00000002, Page 0x00000009
        Target: Writing image data to Block 0x00000002, Page 0x0000000A
        Target: Writing image data to Block 0x00000002, Page 0x0000000B
        Target: Writing image data to Block 0x00000002, Page 0x0000000C
        Target: Writing image data to Block 0x00000002, Page 0x0000000D
        Target: Writing image data to Block 0x00000002, Page 0x0000000E
        Target: Writing image data to Block 0x00000002, Page 0x0000000F
        Target: Writing image data to Block 0x00000002, Page 0x00000010
        Target: Writing image data to Block 0x00000002, Page 0x00000011
        Target: Writing image data to Block 0x00000002, Page 0x00000012
        Target: Writing image data to Block 0x00000002, Page 0x00000013
        Target: Writing image data to Block 0x00000002, Page 0x00000014
        Target: Writing image data to Block 0x00000002, Page 0x00000015
        Target: Writing image data to Block 0x00000002, Page 0x00000016
        Target: Writing image data to Block 0x00000002, Page 0x00000017
        Target: Writing image data to Block 0x00000002, Page 0x00000018
        Target: Writing image data to Block 0x00000002, Page 0x00000019
        Target: Writing image data to Block 0x00000002, Page 0x0000001A
        Target: Writing image data to Block 0x00000002, Page 0x0000001B
        Target: Writing image data to Block 0x00000002, Page 0x0000001C
        Target: Writing image data to Block 0x00000002, Page 0x0000001D
        Target: Writing image data to Block 0x00000002, Page 0x0000001E
        Target: Writing image data to Block 0x00000002, Page 0x0000001F
        Target: Writing image data to Block 0x00000002, Page 0x00000020
        Target: Writing image data to Block 0x00000002, Page 0x00000021
        Target: Writing image data to Block 0x00000002, Page 0x00000022
        Target: Writing image data to Block 0x00000002, Page 0x00000023
        Target: Writing image data to Block 0x00000002, Page 0x00000024
        Target: Writing image data to Block 0x00000002, Page 0x00000025
        Target: Writing image data to Block 0x00000002, Page 0x00000026
        Target: Writing image data to Block 0x00000002, Page 0x00000027
        Target: Writing image data to Block 0x00000002, Page 0x00000028
        Target: Writing image data to Block 0x00000002, Page 0x00000029
        Target: Writing image data to Block 0x00000002, Page 0x0000002A
        Target: Writing image data to Block 0x00000002, Page 0x0000002B
        Target: Writing image data to Block 0x00000002, Page 0x0000002C
        Target: Writing image data to Block 0x00000002, Page 0x0000002D
        Target: Writing image data to Block 0x00000002, Page 0x0000002E
        Target: Writing image data to Block 0x00000002, Page 0x0000002F
        Target: Writing image data to Block 0x00000002, Page 0x00000030
        Target: Writing image data to Block 0x00000002, Page 0x00000031
        Target: Writing image data to Block 0x00000002, Page 0x00000032
        Target: Writing image data to Block 0x00000002, Page 0x00000033
        Target: Writing image data to Block 0x00000002, Page 0x00000034
        Target: Writing image data to Block 0x00000002, Page 0x00000035
        Target: Writing image data to Block 0x00000002, Page 0x00000036
        Target: Writing image data to Block 0x00000002, Page 0x00000037
        Target: Writing image data to Block 0x00000002, Page 0x00000038
        Target: Writing image data to Block 0x00000002, Page 0x00000039
        Target: Writing image data to Block 0x00000002, Page 0x0000003A
        Target: Writing image data to Block 0x00000002, Page 0x0000003B
        Target: Writing image data to Block 0x00000002, Page 0x0000003C
        Target: Writing image data to Block 0x00000002, Page 0x0000003D
        Target: Writing image data to Block 0x00000002, Page 0x0000003E
        Target: Writing image data to Block 0x00000002, Page 0x0000003F
        Target: Writing image data to Block 0x00000003, Page 0x00000000
        Target: Writing image data to Block 0x00000003, Page 0x00000001
        Target: Writing image data to Block 0x00000003, Page 0x00000002
        Target: Writing image data to Block 0x00000003, Page 0x00000003
        Target: Writing image data to Block 0x00000003, Page 0x00000004
        Target: Writing image data to Block 0x00000003, Page 0x00000005
        Target: Writing image data to Block 0x00000003, Page 0x00000006
        Target: Writing image data to Block 0x00000003, Page 0x00000007
        Target: Writing image data to Block 0x00000003, Page 0x00000008
        Target: Writing image data to Block 0x00000003, Page 0x00000009
        Target: Writing image data to Block 0x00000003, Page 0x0000000A
        Target: Writing image data to Block 0x00000003, Page 0x0000000B
        Target: Writing image data to Block 0x00000003, Page 0x0000000C
        Target: Writing image data to Block 0x00000003, Page 0x0000000D
        Target: Writing image data to Block 0x00000003, Page 0x0000000E
        Target: Writing image data to Block 0x00000003, Page 0x0000000F
        Target: Writing image data to Block 0x00000003, Page 0x00000010
        Target: Writing image data to Block 0x00000003, Page 0x00000011
        Target: Writing image data to Block 0x00000003, Page 0x00000012
        Target: Writing image data to Block 0x00000003, Page 0x00000013
        Target: Writing image data to Block 0x00000003, Page 0x00000014
        Target: Writing image data to Block 0x00000003, Page 0x00000015
        Target: Writing image data to Block 0x00000003, Page 0x00000016
        Target: Writing image data to Block 0x00000003, Page 0x00000017
        Target: Writing image data to Block 0x00000003, Page 0x00000018
        Target: Writing image data to Block 0x00000003, Page 0x00000019
        Target: Writing image data to Block 0x00000003, Page 0x0000001A
        Target: Writing image data to Block 0x00000003, Page 0x0000001B
        Target: Writing image data to Block 0x00000003, Page 0x0000001C
        Target: Writing image data to Block 0x00000003, Page 0x0000001D
        Target: Writing image data to Block 0x00000003, Page 0x0000001E
        Target: Writing image data to Block 0x00000003, Page 0x0000001F
        Target: Writing image data to Block 0x00000003, Page 0x00000020
        Target: Writing image data to Block 0x00000003, Page 0x00000021
        Target: Writing image data to Block 0x00000003, Page 0x00000022
        Target: Writing image data to Block 0x00000003, Page 0x00000023
        Target: Writing image data to Block 0x00000003, Page 0x00000024
        Target: Writing image data to Block 0x00000003, Page 0x00000025
        Target: Writing image data to Block 0x00000003, Page 0x00000026
        Target: Writing image data to Block 0x00000003, Page 0x00000027
        Target: Writing image data to Block 0x00000003, Page 0x00000028
        Target: Writing image data to Block 0x00000003, Page 0x00000029
        Target: Writing image data to Block 0x00000003, Page 0x0000002A
        Target: Writing image data to Block 0x00000003, Page 0x0000002B
        Target: Writing image data to Block 0x00000003, Page 0x0000002C
        Target: Writing image data to Block 0x00000003, Page 0x0000002D
        Target: Writing image data to Block 0x00000003, Page 0x0000002E
        Target: Writing image data to Block 0x00000003, Page 0x0000002F
        Target: Writing image data to Block 0x00000003, Page 0x00000030
        Target: Writing image data to Block 0x00000003, Page 0x00000031
        Target: Writing image data to Block 0x00000003, Page 0x00000032
        Target: Writing image data to Block 0x00000003, Page 0x00000033
        Target: Writing image data to Block 0x00000003, Page 0x00000034
        Target: Writing image data to Block 0x00000003, Page 0x00000035
        Target: Writing image data to Block 0x00000003, Page 0x00000036
        Target: Writing image data to Block 0x00000003, Page 0x00000037
        Target: Writing image data to Block 0x00000003, Page 0x00000038
        Target: Writing image data to Block 0x00000003, Page 0x00000039
        Target: Writing image data to Block 0x00000003, Page 0x0000003A
        Target: Writing image data to Block 0x00000003, Page 0x0000003B
        Target: Writing image data to Block 0x00000003, Page 0x0000003C
        Target: Writing image data to Block 0x00000003, Page 0x0000003D
        Target: Writing image data to Block 0x00000003, Page 0x0000003E
        Target: Writing image data to Block 0x00000003, Page 0x0000003F
        Target: Writing image data to Block 0x00000004, Page 0x00000000
        Target: Writing image data to Block 0x00000004, Page 0x00000001
        Target: Writing image data to Block 0x00000004, Page 0x00000002
        Target: Writing image data to Block 0x00000004, Page 0x00000003
        Target: Writing image data to Block 0x00000004, Page 0x00000004
        Target: Writing image data to Block 0x00000004, Page 0x00000005
        Target: Writing image data to Block 0x00000004, Page 0x00000006
        Target: Writing image data to Block 0x00000004, Page 0x00000007
 100%   ������������������������������������������������������������008
                   Application programming complete                   9
        Target:    DONE
        Target:    DONE

Operation completed successfully.

C:\BIOSv4\OMAP-L138_FlashAndBootUtils_2_40\OMAP-L138\GNU>

Thanks

GBL

0 Gaby Levy over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 410 points

Thanks I will try the StarterWare program, I put the data in the site and still not get the approval to download, will retry in several hours.

I programmed it using console , not uart.

As to DipSwitches:

I tried to put the NAND16 state (1 OFF rest ON), still nothing

I tried to put the UART2 state (2 and 4 ON, 1 and 3 OFF) - applicaiotn not startig, I am getting BOOTME in the terminal program. I tried to write there something as jjust carriage return, or help, or "?" but nothing hapens.

Thakns

GBL

0 Titusrathinaraj Stalin over 11 years ago in reply to Gaby Levy

TI__Guru** 116100 points

Hi Gaby,

C:\BIOSv4\OMAP-L138_FlashAndBootUtils_2_40\OMAP-L138\GNU>sfh_OMAP-L138 -flash_n
ubl c:\BIOSv4\Labs\SensorPrj_NAND.bin -flashType NAND -targetType C6748_LCDK -p
COM2 -v

What is this SensorPrj_NAND.bin application DSP/ARM ?

From your logs,

I noticed that you are using "flash_noubl" option and DSP or ARM binary,

I would like to suggest that use "flash" option and mention ARM UBL code and DSP/APP application file(Point No 2) (with entry point if it is DSP app)

1) Flash the memory with a single application image - This will place an application image at address 0x0 of the flash. This must be an AIS format binary, which can be created with the AISgen utilities bundled with the Bootloader User Guide and associated files.

..\sfh_OMAP-L138.exe -flash_noubl <binary application file>

Ex:

..\sfh_OMAP-L138.exe -flash_noubl u-boot.ais

where

u-boot.ais -> u-boot for linux

2) Flash the memory with a UBL and application image - This will place a UBL at address 0x0 of the flash and an application image, such as u-boot, at address 0x10000. In general, a UBL is not required, and this mode is only used when restoring the default flash contents, as explained in the following section.

..\sfh_OMAP-L138.exe -flash <UBL binary file> <binary application file>

Ex:

..\sfh_OMAP-L138.exe -flash ARM-UBL.bin DSP-UBL.bin

where

ARM-UBL.bin -> converted to AIS from .out by AISgen tool

DSP-UBL.bin -> converted to AIS from .out by AISgen tool

http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138#Serial_Flasher_Options

http://processors.wiki.ti.com/index.php/Boot_Images_for_OMAP-L138#Booting_DSP_Binaries

DSP app boot through ARM UBL

http://processors.wiki.ti.com/images/3/32/OMAPL138-DSP-LED-v4.zip

ARM app boot through ARM UBL

http://processors.wiki.ti.com/images/2/26/OMAPL138-ARM-LED-v3.zip

0 Gaby Levy over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 410 points

Hi,

Thanks for your reply... I will try to provide the answers, hope it will help :)

I am using C6748 (DSP, not ARM).

"SensorPrj_NAND.bin" - this is I created using the .out compilation of my project (using release configuration).

I created this using AIS utility, configuration as described here: : http://software-dl.ti.com/trainingTTO/trainingTTO_public_sw/bios/BIOS_14b_Flash.pdf

My project is based on one of the BIOS sample applications (I took one that creates one task and uses a semaphore)... and from it I added NDK and NDS - I created a small TCP server which answers to some TCP commands from single client that connects to it.

So,

I was thinking that I need only to use the AIS, convert my out to bin, then program it to the flash (I did not manage with the SPI writter, long different story, so I used this sfh utility which was easy and quick).

Now, I see in your answer that you wrote that what I used is ok for linux os?

If so, I will need to use the second option as you wrote below...

But how do I create the UBL bin file? what do I take as source and where do I get it from?

Thanks in advance,

GBL

0 Titusrathinaraj Stalin over 11 years ago in reply to Gaby Levy

TI__Guru** 116100 points

Hi,

Sorry for the misinterpretation,

You can flash your DSP app directly on NAND flash if you are using C6748 device.

In case OMAPL138, We need to wakeup the DSP through ARM UBL and can run DSP app in it,

http://processors.wiki.ti.com/index.php/Boot_Images_for_OMAP-L138#C6748_EVM

In this case, only the DSP program is required. The same instructions above apply with a few exceptions

Use the C6748-LED-x.cfg file to create C6748-LED-x.bin. Note that only the DSP application is needed as an input file
When flashing, use the -targetType C6748 option

Download the DSP LED program and try to flash that DSP app on C6748_LCDK or EVM

0 Gaby Levy over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 410 points

Hi,,,

I will write exactly the details:

1) The DS are according to c6748_LCDK which is what I have, so uart are [0123]=[OFF ON OFF ON]

2) I create usin the AIS bin file - for NAND flash 16 bit, this actually helped solving part of the problem.

Currently what I see is that my main starts (I put there some ouput to uart port, I am getting this) however there is a problem with BIOS start (I put in a task an output to the uart, I am not getting it).

Attached is the debug gel data.

As for my map file (if needed), it starts like this:

OUTPUT FILE NAME: <SensorPrj.out>
ENTRY POINT SYMBOL: "_c_int00" address: c0051b80

MEMORY CONFIGURATION

name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
IROM 11700000 00100000 00000000 00100000 R X
IRAM 11800000 00040000 00000000 00040000 RW X
L3_CBA_RAM 80000000 00020000 00000000 00020000 RW X
DDR c0000000 08000000 000ccfdf 07f33021 RWIX

Please advice...

Fullscreen 4774.debug_gel.txt Download

C674X_0: Output: 	Target Connected.
C674X_0: Output: 	---------------------------------------------
C674X_0: Output: 	Memory Map Cleared.
C674X_0: Output: 	---------------------------------------------
C674X_0: Output: 	Memory Map Setup Complete.
C674X_0: Output: 	---------------------------------------------
C674X_0: Output: 	PSC Enable Complete.
C674X_0: Output: 	---------------------------------------------
C674X_0: Output: 	PLL0 init done for Core:300MHz, EMIFA:25MHz
C674X_0: Output: 	DDR initialization is in progress....
C674X_0: Output: 	PLL1 init done for DDR:150MHz
C674X_0: Output: 	Using DDR2 settings
C674X_0: Output: 	DDR2 init for 150 MHz is done
C674X_0: Output: 	---------------------------------------------
C674X_0: GEL Output: 
---------------------------------------------
C674X_0: GEL Output: |             Device Information            |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x00000010
C674X_0: GEL Output: DEV_INFO_03 = 0x00000003
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6544787-11-11-16
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 3,0,0,874
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3830306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x0B01000B
C674X_0: GEL Output: DEV_INFO_25 = 0x0063DD93
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x06D40003
C674X_0: GEL Output: 

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |               BOOTROM Info                |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k008 
C674X_0: GEL Output: Silicon Revision 2.1
C674X_0: GEL Output: Boot pins: 16
C674X_0: GEL Output: Boot Mode: NAND 16
C674X_0: GEL Output: 
ROM Status Code: 0x00000000 
Description:C674X_0: GEL Output: No error
C674X_0: GEL Output: 
Program Counter (PC) = 0xC00319D8
C674X_0: GEL Output: 
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              Clock Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: 
C674X_0: GEL Output: PLLs configured to utilize crystal.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output: 
C674X_0: GEL Output: NOTE:  All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 24 MHz.  If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output: 
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: 
C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
C674X_0: GEL Output: 
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: 
C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
C674X_0: GEL Output: 
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: 
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output: 
C674X_0: GEL Output: Module 0:	EDMA3CC (0)        STATE = 3
C674X_0: GEL Output: Module 1:	EDMA3 TC0          STATE = 3
C674X_0: GEL Output: Module 2:	EDMA3 TC1          STATE = 3
C674X_0: GEL Output: Module 3:	EMIFA (BR7)        STATE = 3
C674X_0: GEL Output: Module 4:	SPI 0              STATE = 3
C674X_0: GEL Output: Module 5:	MMC/SD 0           STATE = 3
C674X_0: GEL Output: Module 6:	AINTC              STATE = 3
C674X_0: GEL Output: Module 7:	ARM RAM/ROM        STATE = 3
C674X_0: GEL Output: Module 9:	UART 0             STATE = 3
C674X_0: GEL Output: Module 10:	SCR 0 (BR0/1/2/8)  STATE = 3
C674X_0: GEL Output: Module 11:	SCR 1 (BR4)        STATE = 3
C674X_0: GEL Output: Module 12:	SCR 2 (BR3/5/6)    STATE = 3
C674X_0: GEL Output: Module 13:	PRUSS              STATE = 0
C674X_0: GEL Output: Module 14:	ARM                STATE = 0
C674X_0: GEL Output: Module 15:	DSP                STATE = 3
C674X_0: GEL Output: 
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: 
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output: 
C674X_0: GEL Output: Module 0:	EDMA3CC (1)        STATE = 3
C674X_0: GEL Output: Module 1:	USB0 (2.0)         STATE = 3
C674X_0: GEL Output: Module 2:	USB1 (1.1)         STATE = 3
C674X_0: GEL Output: Module 3:	GPIO               STATE = 3
C674X_0: GEL Output: Module 4:	UHPI               STATE = 3
C674X_0: GEL Output: Module 5:	EMAC               STATE = 3
C674X_0: GEL Output: Module 6:	DDR2 and SCR F3    STATE = 3
C674X_0: GEL Output: Module 7:	MCASP0 + FIFO      STATE = 3
C674X_0: GEL Output: Module 8:	SATA               STATE = 3
C674X_0: GEL Output: Module 9:	VPIF               STATE = 3
C674X_0: GEL Output: Module 10:	SPI 1              STATE = 3
C674X_0: GEL Output: Module 11:	I2C 1              STATE = 3
C674X_0: GEL Output: Module 12:	UART 1             STATE = 3
C674X_0: GEL Output: Module 13:	UART 2             STATE = 3
C674X_0: GEL Output: Module 14:	MCBSP0 + FIFO      STATE = 3
C674X_0: GEL Output: Module 15:	MCBSP1 + FIFO      STATE = 3
C674X_0: GEL Output: Module 16:	LCDC               STATE = 3
C674X_0: GEL Output: Module 17:	eHRPWM (all)       STATE = 3
C674X_0: GEL Output: Module 18:	MMC/SD 1           STATE = 3
C674X_0: GEL Output: Module 19:	UPP                STATE = 3
C674X_0: GEL Output: Module 20:	eCAP (all)         STATE = 3
C674X_0: GEL Output: Module 21:	EDMA3 TC2          STATE = 3
C674X_0: GEL Output: Module 24:	SCR-F0 Br-F0       STATE = 3
C674X_0: GEL Output: Module 25:	SCR-F1 Br-F1       STATE = 3
C674X_0: GEL Output: Module 26:	SCR-F2 Br-F2       STATE = 3
C674X_0: GEL Output: Module 27:	SCR-F6 Br-F3       STATE = 3
C674X_0: GEL Output: Module 28:	SCR-F7 Br-F4       STATE = 3
C674X_0: GEL Output: Module 29:	SCR-F8 Br-F5       STATE = 3
C674X_0: GEL Output: Module 30:	Br-F7 (DDR Contr)  STATE = 3
C674X_0: GEL Output: Module 31:	L3 RAM, SCR-F4, Br-F6 STATE = 3

0 Gaby Levy over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 410 points

Hi,

Eventually I managed to solve this way:

1) I had incorrect flash configuration in the ais gen (needed to be 16)

2) Important: The ais gen does not save correctly the PSC1 values, so those that were configured before were not there.... this is why when I activated part of the bios the app stopped working.

In order to "fix this" I edited manually the configuration file...

Anyway those are the values:

LPSC0 Enable=0+1+2+3+4+5+6+9+10+11+12+15
LPSC1 Enable=0+1+2+3+4+5+6+7+9+10+11+12+13+14+15+16+17+18+19+20+21+24+25+26+27+28+29+30+31

Thanks for all...

GBL

0 Titusrathinaraj Stalin over 11 years ago in reply to Gaby Levy

TI__Guru** 116100 points

Hi,

Thanks for your update.

Processors

Processors forum

sfh_OMAP-L138 - problem detecting the board