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status profiling of second CPU in SMP processor

Ramesh071
Intellectual 620 points


Hi,

I'm working on TI's DRA7XX SMP processor.


It is having dual cores. I'm seeing the profiling status of first CPU using the bootchart  at the time of booting.

In similar way I want profile the status of the second CPU at booting time.


Is is possible to profile the status of 2nd CPU at the boot time, If yes how can I do this.

Kindly help me to resolve this issue.

Thanks

Ramappa

  • 0
    TI__Mastermind 29520 points

    Hello Ramappa,

    About your question:

    U-boot is only executed on cpu 0.  The other cores are placed in stand-by by the boot monitor, and are awoken by the kernel.

    ROM code: Responsible for finding, for downloading, and for executing the initial software by using the
    master CPU

    Master CPU: The ARM® CortexTM-A15 MPCoreTM CPU for which CPU-ID is 0. It configures the multicore platform and starts the ROM code to ensure device booting from a mass storage memory (memory booting) or a peripheral interface (peripheral booting).

    Slave CPU: The ARM Cortex-A15 MPCore CPU for which CPU-ID is 1. It is brought to the wait-for- event (WFE) state by the ROM code, waiting to be woken up by the master CPU.

    Wake-up generator (MPU_WUGEN):
    – Used by the ROM code and OS during SMP boot
    Standby controller: Handles the power transitions inside the MPU subsystem Realtime (master) counter (COUNTER_REALTIME)

    MPU_WUGEN includes two registers (AUX_CORE_BOOT0 and AUX_CORE_BOOT1) which can be used
    by the ROM code and OS during SMP boot. The AUX_CORE_BOOT0 register is intended to indicate boot
    status to either cores; the AUX_CORE_BOOT1 register can be used to store execution start address of
    the second core (also known as aux core).

    The realtime counter (COUNTER_REALTIME), also called master counter, is a free-running counter, which is related to real time.

    See the CPU configurations in following files of DRA7xx GLSDK:
    arch/arm/mach-omap2/omap-headsmp.S
    arch/arm/mach-omap2/omap-hotplug.c

    arch/arm/mach-omap2/omap-smp.c

    arch/arm/mach-omap2/omap-wakeupgen.c

    See SMP boot registers - AUX_CORE_BOOT_0 and AUX_CORE_BOOT_1 in DRA7xx TRM.

    Best regards,

    Yanko

  • 0 in reply to Yanko Todorov-XID
    Intellectual 620 points

    Hi,

    Thanks Yanko..!! It is detailed one and clear.

    Now my question is, Is there any way to wake up the other core at the earlier stage.

    like in u-boot is it possible to enable the second core?,  so that from u-boot I need to keep both the cores busy.

    Kindly send me your approach on above case.

    Thanks

    Ramappa

  • 0 in reply to Ramesh071
    TI__Mastermind 29520 points

    Hello Ramappa,

    The u-boot is a second stage bootloader that is loaded by the x-loader into DDR. It comes from Das U-Boot. The u-boot can perform CPU dependent and board dependent initialization and configuration not done in the x-loader. The u-boot also includes fastboot functionality for partitioning and flashing the eMMC. The u-boot runs on the Master CPU (CPU ID 0), which is responsible for the initialization and booting; at the same time, the Slave CPU (CPU ID 1) is held in the “wait for event” state.

    See the following file - /u-boot/arch/arm/cpu/armv7/ start.S

    Best regards,

    Yanko