Some questions about C6747's McASP

Hello:

    I configured mcasp0 to TDM mode: I2S mode,slot size is 32 bit,configured srctl0 to receiver and configured srctl6 to transmiter.

   In main function ,if I write data in xbuf6,then rbuf6 changes to the same data.why?

   And there are always 0 in rbuf0, rstat is 0x171.why?

   Rstat is  cleared by writing 1,but in main function it can not be cleard even though I write 1.why?

   In  interrupt  function,can not receive data,initialization and interrupt function are as follows:

Initialization:

mcasp0Regs->GBLCTL=0;
mcasp0Regs->RGBLCTL=0;
mcasp0Regs->XGBLCTL=0;
//mcasp0Regs->PWRDEMU=1;
// mcasp0Regs->DLBCTL=0x07;

mcasp0AfifoRegs->WFIFOCTL = CSL_AFIFO_WFIFOCTL_WENA_DISABLED; //Write FIFO is disabled.
mcasp0AfifoRegs->RFIFOCTL = CSL_AFIFO_RFIFOCTL_RENA_DISABLED;

/*******工作模式配置*****************/
/************RX**********************/
mcasp0Regs->RMASK=0xFFFFFFFF; // All bit enable
mcasp0Regs->RFMT = (0<<16 | 1<<15 | 0xF<<4 | 1<<3 | 0);

//接收帧同步：TDM（I2S） mode；接收帧同步宽度：一个字宽；外部产生；上升沿表示帧的开始。
mcasp0Regs->AFSRCTL = (CSL_MCASP_AFSRCTL_RMOD_I2S << CSL_MCASP_AFSRCTL_RMOD_SHIFT)|\
(CSL_MCASP_AFSRCTL_FRWID_WORD << CSL_MCASP_AFSRCTL_FRWID_SHIFT)|\
(CSL_MCASP_AFSRCTL_FSRM_EXTERNAL << CSL_MCASP_AFSRCTL_FSRM_SHIFT)|\
(CSL_MCASP_AFSRCTL_FSRP_FALLINGEDGE << CSL_MCASP_AFSRCTL_FSRP_SHIFT);

//接收时钟控制：接收器在串行时钟的上升沿采样数据；外部接收时钟源；接收位时钟分频比为:1
/* mcasp0Regs->ACLKRCTL = (CSL_MCASP_ACLKRCTL_CLKRP_FALLINGEDGE << CSL_MCASP_ACLKRCTL_CLKRP_SHIFT)|\
(CSL_MCASP_ACLKRCTL_CLKRM_INTERNAL << CSL_MCASP_ACLKRCTL_CLKRM_SHIFT)|\
(0x03 << CSL_MCASP_ACLKRCTL_CLKRDIV_SHIFT);*/
//接收时钟检查控制寄存器
//mcasp0Regs->RCLKCHK = CSL_MCASP_RCLKCHK_RESETVAL;// RCLKCHK0=0xFF000F; // Doesn't care

//接收高频时钟控制：外部时钟源；接收位流高频时钟极性：上升沿，不翻转；接收高频时钟分配比:1
mcasp0Regs->AHCLKRCTL = (CSL_MCASP_AHCLKRCTL_HCLKRM_EXTERNAL << CSL_MCASP_AHCLKRCTL_HCLKRM_SHIFT)|\
(CSL_MCASP_AHCLKRCTL_HCLKRP_NOTINVERTED << CSL_MCASP_AHCLKRCTL_HCLKRP_SHIFT)|\
(0x00 << CSL_MCASP_AHCLKRCTL_HCLKRDIV_SHIFT);//AHCLKR0=24.576MHz/2=12.288MHz
//接收TDM时隙寄存器：slot0,slot1是活跃的
mcasp0Regs->RTDM = (Uint32) 0x03;

//接收中断控制寄存器:中断全部使能
mcasp0Regs->RINTCTL = 0x00000020;
mcasp0Regs->RCLKCHK = 0x00FF0008;
//EDMA EVENT GENERATE
//mcasp0Regs->XEVTCTL = CSL_MCASP_XEVTCTL_XDATDMA_ENABLE;
/***** TX *****/
mcasp0Regs->XMASK = (Uint32) 0xFFFFFFFF; //发送数据所有位都不屏蔽.
mcasp0Regs->XFMT = (0<<16 | 1<<15 | 0xF<<4 | 1<<3 | 0); //发送位延迟： 0位延迟
//接收串行位流顺序：MSB先发送
//时隙大小为32位
//Reads from XRBUF[n] originate on the DMA port.
//no rotation.
//mcasp0Regs->XEVTCTL = CSL_MCASP_XEVTCTL_XDATDMA_ENABLE;
//发送帧同步：TDM（I2S） mode；发送帧同步宽度：一个字宽；外部产生；上升沿表示帧的开始。
mcasp0Regs->AFSXCTL = (CSL_MCASP_AFSXCTL_XMOD_I2S << CSL_MCASP_AFSXCTL_XMOD_SHIFT)|\
(CSL_MCASP_AFSXCTL_FXWID_WORD << CSL_MCASP_AFSXCTL_FXWID_SHIFT)|\
(CSL_MCASP_AFSXCTL_FSXM_INTERNAL << CSL_MCASP_AFSXCTL_FSXM_SHIFT)|\
(CSL_MCASP_AFSXCTL_FSXP_FALLINGEDGE << CSL_MCASP_AFSXCTL_FSXP_SHIFT);
//发送时钟控制：发送器在串行时钟的上升沿发送数据；发送和接收同步外部接收时钟源；发送位时钟分频比为:4
mcasp0Regs->ACLKXCTL = (CSL_MCASP_ACLKXCTL_CLKXP_FALLINGEDGE << CSL_MCASP_ACLKXCTL_CLKXP_SHIFT)|\
(CSL_MCASP_ACLKXCTL_ASYNC_SYNC << CSL_MCASP_ACLKXCTL_ASYNC_SHIFT)|\
(CSL_MCASP_ACLKXCTL_CLKXM_INTERNAL << CSL_MCASP_ACLKXCTL_CLKXM_SHIFT)|\
(0x03 << CSL_MCASP_ACLKXCTL_CLKXDIV_SHIFT);
//发送时钟检查控制寄存器
//mcasp0Regs->XCLKCHK = 0x00FF0008;//CSL_MCASP_XCLKCHK_RESETVAL; //CLKCHK0=0xFF000F; // Doesn't care

//发送高频时钟控制：外部时钟源；发送位流高频时钟极性：上升沿，不翻转；发送高频时钟分配比:2
mcasp0Regs->AHCLKXCTL = (CSL_MCASP_AHCLKXCTL_HCLKXM_INTERNAL << CSL_MCASP_AHCLKXCTL_HCLKXM_SHIFT)|\
(CSL_MCASP_AHCLKXCTL_HCLKXP_NOTINVERTED << CSL_MCASP_AHCLKXCTL_HCLKXP_SHIFT)|\
(0x01 << CSL_MCASP_AHCLKXCTL_HCLKXDIV_SHIFT);
//发送TDM时隙寄存器：slot0,slot1是活跃的
mcasp0Regs->XTDM = (Uint32) 0x03;

//发送中断控制寄存器:中断全部使能
mcasp0Regs->XINTCTL = 0x00000020;
mcasp0Regs->XCLKCHK = 0x00FF0008;
//EDMA EVENT GENERATE
//mcasp0Regs->REVTCTL = CSL_MCASP_REVTCTL_RDATDMA_RSV;

/******************串口配置***************************/

//AXR0[0],AXR0[1]为接收器
mcasp0Regs->SRCTL0 = (CSL_MCASP_SRCTL0_SRMOD_RCV << CSL_MCASP_SRCTL0_SRMOD_SHIFT);
//mcasp0Regs->SRCTL1 = (CSL_MCASP_SRCTL0_SRMOD_RCV << CSL_MCASP_SRCTL1_SRMOD_SHIFT);
//AXR0[5],AXR0[6]为发送器
mcasp0Regs->SRCTL6 = (CSL_MCASP_SRCTL6_SRMOD_XMT << CSL_MCASP_SRCTL6_SRMOD_SHIFT);
//mcasp0Regs->SRCTL0 = (CSL_MCASP_SRCTL0_SRMOD_XMT << CSL_MCASP_SRCTL0_SRMOD_SHIFT);

/*****LOOPBACK*****/

/*****配置输入输出引脚*****AXR00---输出，AXR01---输入**********/
// both transmit and receiver use the same FS and BCLK

//将MCASP0所有管脚均用做MCASP引脚
mcasp0Regs->PFUNC = CSL_MCASP_PFUNC_RESETVAL;
//mcasp0Regs->PDIR =0x1C000040;
//LOOPBACK
mcasp0Regs->PDIR =0x1C000001;

mcasp0Regs->DITCTL = 0x00000000; // Not used
mcasp0Regs->DLBCTL = 0x00000000; // Not used
mcasp0Regs->AMUTE = 0x00000000;

/************ Step 3: reset AHCLK **************/
//******a.Take the respective internal high-frequency serial clock divider(s) out of reset
mcasp0Regs->RGBLCTL = (CSL_MCASP_RGBLCTL_RHCLKRST_ACTIVE << CSL_MCASP_RGBLCTL_RHCLKRST_SHIFT);

//******b.Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
//GBLCTL before you proceed.
while(!(mcasp0Regs->RGBLCTL & 0x0002));

//******a.Take the respective internal high-frequency serial clock divider(s) out of reset
mcasp0Regs->XGBLCTL |= (CSL_MCASP_XGBLCTL_XHCLKRST_ACTIVE << CSL_MCASP_XGBLCTL_XHCLKRST_SHIFT);

//******b.Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
//GBLCTL before you proceed.
while(!(mcasp0Regs->XGBLCTL & 0x0200));

/************Step 4: reset ACLK **************/
//******a.Take the respective internal serial clock divider(s) out of reset

mcasp0Regs->RGBLCTL |= (CSL_MCASP_RGBLCTL_RCLKRST_ACTIVE << CSL_MCASP_RGBLCTL_RCLKRST_SHIFT);

//******b.Read back from GBLCTL
while(!(mcasp0Regs->RGBLCTL & 0x0001));

//******a.Take the respective internal serial clock divider(s) out of reset
mcasp0Regs->XGBLCTL |= (CSL_MCASP_XGBLCTL_XCLKRST_ACTIVE << CSL_MCASP_XGBLCTL_XCLKRST_SHIFT);

//******b.Read back from GBLCTL
while(!(mcasp0Regs->XGBLCTL & 0x0100));

//EDMA3_SendInitialCfg();
//EDMA3_ReceiveStartCfg();
//mcasp0Regs->RINTCTL = 0x00000020;

// Step 6: 激活串行器
mcasp0Regs->XSTAT = (Uint32) 0xFFFF;
mcasp0Regs->RSTAT = (Uint32) 0xFFFF;

//******b.Take the respective serializers out of reset
mcasp0Regs->XGBLCTL |= (CSL_MCASP_XGBLCTL_XSRCLR_ACTIVE << CSL_MCASP_XGBLCTL_XSRCLR_SHIFT);

//******c.Read back from GBLCTL
while(!(mcasp0Regs->XGBLCTL & 0x0400));

//******b.Take the respective serializers out of reset
mcasp0Regs->RGBLCTL |= (CSL_MCASP_RGBLCTL_RSRCLR_ACTIVE << CSL_MCASP_RGBLCTL_RSRCLR_SHIFT);

//******c.Read back from GBLCTL
while(!(mcasp0Regs->RGBLCTL & 0x0004));

//mcasp0Regs->XBUF6 = 0x89649548;
//mcasp0Regs->RBUF0 = 0x58755639;

// Step 8: 状态机退出复位

//******a.Take the respective state machine(s) out of reset
mcasp0Regs->RGBLCTL |= (CSL_MCASP_RGBLCTL_RSMRST_ACTIVE << CSL_MCASP_RGBLCTL_RSMRST_SHIFT);

//******b.Read back from GBLCTL
while(!(mcasp0Regs->RGBLCTL & 0x0008));

//******a.Take the respective state machine(s) out of reset
mcasp0Regs->XGBLCTL |= (CSL_MCASP_XGBLCTL_XSMRST_ACTIVE << CSL_MCASP_XGBLCTL_XSMRST_SHIFT);

//******b.Read back from GBLCTL
while(!(mcasp0Regs->XGBLCTL & 0x0800));

// Step 9 帧同步信息退出复位

//******a.Take the respective frame sync generator(s) out of reset
mcasp0Regs->RGBLCTL |= (CSL_MCASP_RGBLCTL_RFRST_ACTIVE << CSL_MCASP_RGBLCTL_RFRST_SHIFT);

//******b.Read back from GBLCTL
while(!(mcasp0Regs->RGBLCTL & 0x0010));

//******a.Take the respective frame sync generator(s) out of reset
mcasp0Regs->XGBLCTL |= (CSL_MCASP_XGBLCTL_XFRST_ACTIVE << CSL_MCASP_XGBLCTL_XFRST_SHIFT);

//******b.Read back from GBLCTL
while(!(mcasp0Regs->XGBLCTL & 0x1000));

interrupt void Interrupt4(void)
{

mcasp0Regs->RSTAT |= 0x20;
ICR = 0x10;

rcv[cnt++]= mcasp0Regs->RBUF0 ;
if(cnt>=64)
cnt=0;
}