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VPSS MUXSEL cannot set to PCLK

Tim Liebau
Prodigy 60 points


Hello,

We (believe we) are seeing issues with our output and input being out of phase.  We would like to try to use PCLK for clocking both the VPFE and VPBE.

BUT...I cannot set VPSS_CLK_CTRL.VPSS_MUXSEL to 3h.  Why??

Every entry gives me a '1' as follows:

write 3 => 1

write 2 => 0

write 1 => 1

write 0 => 0

It seems like bit '1' is stuck low...is it my processor??  Everything else is working.  Do I have to adjust another setting before the processor will allow me to use PCLK?

Thanks!

Tim Liebau

  • 0
    TI__Mastermind 41665 points

    Which device are you using, I am guessing DM355?

    I don't believe there are any hardware prerequisites to setting VPSS_MUXSEL to use PCLK or EXTCLK, you should be able to set the bit. The only potential prerequisite that may come into play would be the VPSS being disabled when changing the clock input, I am not sure if the VPSS will allow you to change the clock source on the fly.

    One other thought would be to check how you are setting the bit, if you are setting this through some existing C structure it is possible that the code does not allow for the PCLK or EXTCLK modes, it may be worth trying to poke the register directly with a pointer, or investigating this through CCS/JTAG.