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AM335x PLL Configuration Order

Daisuke Maeda
Guru 20205 points
Other Parts Discussed in Thread: CLOCKTREETOOL

Is there the order of PLLs (MPU, Core, Display, DDR, Peripheral) Configuration?

For example: The Core PLL must be configured before other PLLs are configured.

Best regards,

Daisuke

 

  • 0
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    Most of the PLLs are configured initially by ROM code. See section 26.1.4.3 of the AM335X TRM Rev. J.
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    I understand that a user can go without knowing the procedure to configure the PLLs in the initialization.

    Best regards,

    Daisuke

     

  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Our customer wants to reconfigure the PLLs in the user bootloader such as the attached source codes.

    Fullscreen 8424.hw_init.c Download 
    /*************************************************************************
 * Function Name: InitCorePLL
 * Parameters: None
 *
 * Return: None
 *
 * Description: Inits Core DPLL. CLKDCOLDO      2000MHZ
 *                               CORE_CLKOUTM6  500MHz
 *                               CORE_CLKOUTM4  200MHz
 *                               CORE_CLKOUTM5  250MHz
 *
 *************************************************************************/
void InitCorePLL(void)
{
  /*CORE_DPLL in baypass*/
  CM_CLKMODE_DPLL_CORE_bit.DPLL_EN = 4;
  /*Wait DPLL enter bypass mode*/
  while((1 == CM_IDLEST_DPLL_CORE_bit.ST_DPLL_CLK) || 
        (0 == CM_IDLEST_DPLL_CORE_bit.ST_MN_BYPASS));
  /*disable Spread Spectrum Clocking*/
  CM_CLKMODE_DPLL_CORE_bit.DPLL_SSC_EN = 0; 
  /*Set DPLL multiplier factor *1000*/
  CM_CLKSEL_DPLL_CORE_bit.DPLL_MULT = 1000;
  /*Set DPLL divider factor*/
  CM_CLKSEL_DPLL_CORE_bit.DPLL_DIV = 24-1;
  /*Set DPLL post-divider factor M4*/
  CM_DIV_M4_DPLL_CORE_bit.HSDIVIDER_CLKOUT1_DIV = 10;
  /*Set DPLL post-divider factor M5*/
  CM_DIV_M5_DPLL_CORE_bit.HSDIVIDER_CLKOUT2_DIV = 8;
  /*Set DPLL post-divider factor M5*/
  CM_DIV_M6_DPLL_CORE_bit.HSDIVIDER_CLKOUT3_DIV = 4;
  /*CORE_DPLL in baypass*/
  CM_CLKMODE_DPLL_CORE_bit.DPLL_EN = 7;
  /*Wait DPLL locks*/
  while((0 == CM_IDLEST_DPLL_CORE_bit.ST_DPLL_CLK) || 
        (1 == CM_IDLEST_DPLL_CORE_bit.ST_MN_BYPASS));
}

/*************************************************************************
 * Function Name: InitMPUPLL
 * Parameters: None
 *
 * Return: None
 *
 * Description: Inits MPU DPLL.  MPU Clock 600 or 800MHz
 *                               
 *
 *************************************************************************/
void InitMPUPLL(void)
{
  /*MPU_DPLL in baypass*/
  CM_CLKMODE_DPLL_MPU_bit.DPLL_EN = 4;
  /*Wait DPLL enter bypass mode*/
  while((1 == CM_IDLEST_DPLL_MPU_bit.ST_DPLL_CLK) || 
        (0 == CM_IDLEST_DPLL_MPU_bit.ST_MN_BYPASS));
  /*disable Spread Spectrum Clocking*/
  CM_CLKMODE_DPLL_MPU_bit.DPLL_SSC_EN = 0; 
  /*Set DPLL multiplier factor */
  if (ismpuclk() == ON) {
	  CM_CLKSEL_DPLL_MPU_bit.DPLL_MULT = 600;	/* 600MHz */
  } else {
	  CM_CLKSEL_DPLL_MPU_bit.DPLL_MULT = 800;	/* 800MHz */
  }
  /*Set DPLL divider factor*/
  CM_CLKSEL_DPLL_MPU_bit.DPLL_DIV = 24-1;
  /*Set DPLL post-divider factor M2*/
  CM_DIV_M2_DPLL_MPU_bit.DPLL_CLKOUT_DIV = 1;
  /*MPU_DPLL in baypass*/
  CM_CLKMODE_DPLL_MPU_bit.DPLL_EN = 7;
  /*Wait DPLL locks*/
  while((0 == CM_IDLEST_DPLL_MPU_bit.ST_DPLL_CLK) || 
        (1 == CM_IDLEST_DPLL_MPU_bit.ST_MN_BYPASS));
}

/*************************************************************************
 * Function Name: InitPERPLL
 * Parameters: None
 *
 * Return: None
 *
 * Description: Inits PER DPLL.  CLKDCOLDO 960MHZ
 *                               CLKOUT    192MHZ
 *
 *************************************************************************/
void InitPERPLL(void)
{
  /*MPU_DPLL in baypass*/
  CM_CLKMODE_DPLL_PER_bit.DPLL_EN = 4;
  /*Wait DPLL enter bypass mode*/
  while((1 == CM_IDLEST_DPLL_PER_bit.ST_DPLL_CLK) || 
        (0 == CM_IDLEST_DPLL_PER_bit.ST_MN_BYPASS));
  /*disable Spread Spectrum Clocking*/
  CM_CLKMODE_DPLL_PER_bit.DPLL_SSC_EN = 0; 
  /*Set DPLL multiplier factor *960*/
  CM_CLKSEL_DPLL_PERIPH_bit.DPLL_MULT = 960;
  /*Set DPLL divider factor*/
  CM_CLKSEL_DPLL_PERIPH_bit.DPLL_DIV = 24-1;
  /*Set DPLL Sigma-Delta divider*/
  CM_CLKSEL_DPLL_PERIPH_bit.DPLL_SD_DIV = 4;
  /*Set DPLL post-divider factor M2*/
  CM_DIV_M2_DPLL_PER_bit.DPLL_CLKOUT_DIV = 5;
  /*MPU_DPLL in baypass*/
  CM_CLKMODE_DPLL_PER_bit.DPLL_EN = 7;
  /*Wait DPLL locks*/
  while((0 == CM_IDLEST_DPLL_PER_bit.ST_DPLL_CLK) || 
        (1 == CM_IDLEST_DPLL_PER_bit.ST_MN_BYPASS));
}

/*************************************************************************
 * Function Name: InitDDRPLL
 * Parameters: None
 *
 * Return: None
 *
 * Description: Inits DDR DPLL.  DDR Clock 400MHZ
 *                               
 *
 *************************************************************************/
void InitDDRPLL(void)
{
  /*DDR DPLL in baypass*/
  CM_CLKMODE_DPLL_DDR_bit.DPLL_EN = 4;
  /*Wait DPLL enter bypass mode*/
  while((1 == CM_IDLEST_DPLL_DDR_bit.ST_DPLL_CLK) || 
        (0 == CM_IDLEST_DPLL_DDR_bit.ST_MN_BYPASS));
  /*disable Spread Spectrum Clocking*/
  CM_CLKMODE_DPLL_DDR_bit.DPLL_SSC_EN = 0; 
  /*Set DPLL multiplier factor *400*/
  CM_CLKSEL_DPLL_DDR_bit.DPLL_MULT = 400;
  /*Set DPLL divider factor*/
  CM_CLKSEL_DPLL_DDR_bit.DPLL_DIV = 24-1;
  /*Set DPLL post-divider factor M2*/
  CM_DIV_M2_DPLL_MPU_bit.DPLL_CLKOUT_DIV = 1;
  /*MPU_DPLL in baypass*/
  CM_CLKMODE_DPLL_DDR_bit.DPLL_EN = 7;
  /*Wait DPLL locks*/
  while((0 == CM_IDLEST_DPLL_DDR_bit.ST_DPLL_CLK) || 
        (1 == CM_IDLEST_DPLL_DDR_bit.ST_MN_BYPASS));
}

/*************************************************************************
 * Function Name: InitDDR
 * Parameters: None
 *
 * Return: None
 *
 * Description: 
 *                               
 *
 *************************************************************************/
void InitDDR(void)
{
  /*Enable Clocks*/
  CM_PER_L3_CLKSTCTRL_bit.CLKTRCTRL = 2;
  CM_PER_L3_CLKCTRL_bit.MODULEMODE = 2;
  /*Enable Func Clock*/
  CM_PER_EMIF_CLKCTRL_bit.MODULEMODE = 2;
  /*Wait clock to get active*/
  while(CM_PER_EMIF_CLKCTRL_bit.IDLEST);
  /*VTP Init*/
  /*Dynamic VTP compensation mode*/
  VTP_CTRL_bit.ENABLE = 1;
  /*clears flops, start count again*/
  VTP_CTRL_bit.CLRZ = 0;
  VTP_CTRL_bit.CLRZ = 1;
  /*wait ready*/
  while(!VTP_CTRL_bit.READY);
  /*DDR Phy CMD0*/
  CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 = 0x80;
  CMD0_REG_PHY_DLL_LOCK_DIFF_0 = 0x1;
  CMD0_REG_PHY_INVERT_CLKOUT_0 = 0x0;
  /*DDR Phy CMD1*/
  CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 = 0x80;
  CMD1_REG_PHY_DLL_LOCK_DIFF_0 = 0x1;
  CMD1_REG_PHY_INVERT_CLKOUT_0 = 0x0;
  /*DDR Phy CMD2*/
  CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 = 0x80;
  CMD2_REG_PHY_DLL_LOCK_DIFF_0 = 0x1;
  CMD2_REG_PHY_INVERT_CLKOUT_0 = 0x0;
  /*Init Data Macro 0*/
  DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 = 0x40;
  DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 = 0x00;
  DATA0_REG_PHY_WRLVL_INIT_RATIO_0 = 0x0;
  DATA0_REG_PHY_GATELVL_INIT_RATIO_0 = 0x0;
  DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 = 0x7B;
  DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 = 0x80;
  DATA0_REG_PHY_DLL_LOCK_DIFF_0 = 1;
  /*Init Data Macro 1*/
  DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0 = 0x40;
  DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0 = 0x0;
  DATA1_REG_PHY_WRLVL_INIT_RATIO_0 = 0x0;
  DATA1_REG_PHY_GATELVL_INIT_RATIO_0 = 0x0;
  DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 = 0x7B;
  DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0 = 0x80;
  DATA1_REG_PHY_DLL_LOCK_DIFF_0 = 1;
  /**/
  DDR_CMD0_IOCTRL = 0x16B;
  DDR_CMD1_IOCTRL = 0x16B;
  DDR_CMD2_IOCTRL = 0x16B;
  DDR_DATA0_IOCTRL = 0x16B;
  DDR_DATA1_IOCTRL = 0x16B;
  /**/
  DDR_IO_CTRL_bit.DDR3_RST_DEF_VAL = 0;
  DDR_IO_CTRL_bit.DDR_WUCLK_DISABLE = 0;
  DDR_IO_CTRL_bit.MDDR_SEL = 0;
  DDR_CKE_CTRL_bit.DDR_CKE_CTRL = 1;
  /**/
  EMIF_DDR_PHY_CTRL_1 = 0x00000037;
  EMIF_DDR_PHY_CTRL_1_SHDW = 0x00000037;
  /**/
  EMIF_SDRAM_TIM_1 = 0x199DFB1B;
  EMIF_SDRAM_TIM_1_SHDW = 0x199DFB1B;
  EMIF_SDRAM_TIM_2 = 0x269E7FDA;
  EMIF_SDRAM_TIM_2_SHDW = 0x269E7FDA;
  EMIF_SDRAM_TIM_3 = 0x501F895F;
  EMIF_SDRAM_TIM_3_SHDW = 0x501F895F;
  EMIF_SDRAM_REF_CTRL = 0x00000C30;
  EMIF_SDRAM_REF_CTRL_SHDW = 0x00000C30;
  EMIF_ZQ_CONFIG = 0x50074BE4;
  EMIF_SDRAM_CONFIG = 0x60A452B2;

}

/******************************************************************
    Hardware dependent device initialization
 ******************************************************************/

void hw_init(void)

	/*Core PLL init*/
	InitCorePLL();
	/*MPU Clock init*/
	InitMPUPLL();
	/*Peripheral Clock init*/
	InitPERPLL();
	/*DDR PLL Init*/
	InitDDRPLL();
	/*DDR Init*/
	InitDDR();

    return;
}


/********************************< end of file >*******************************/
/* vi:set ts=4 sw=4: */

    Is there the required procedure to configure the PLLs (MPU, Core, Display, DDR, Peripheral)?

    They use the Master Osc (CLK_M_OSC) as the input clock source of all PLLs.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points

    Sorry, I cannot help on software.

  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    You do not necessarily have to watch the source codes. The customer wants to know the PLLs configuration requirements.

    Can you answer the question same as my original question?

    Daisuke Maeda said:

    Is there the order of PLLs (MPU, Core, Display, DDR, Peripheral) Configuration?

    For example: The Core PLL must be configured before other PLLs are configured.

    They use the Master Osc (CLK_M_OSC) as the input clock source of all PLLs.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points

    There is no specific order. It will depend on what peripherals are used and from which clock source they are clocked. I suggest your customer use the AM335X Clock Tree Tool: http://www.ti.com/tool/clocktreetool

  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    Best regards,

    Daisuke