• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 737 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

HPI problem in 6713 DSK

Bing Han1
Prodigy 20 points

Hello,

I would like to use MSP430 F5529 launchpad to control 6713 DSK with HPI. I can access HPIC, HPIA and HPID. However, the memory of DSP cannot update the value if I write HPID and I also cannot read the value of memory from HPID.

I program MSP430 to perform the following steps:

(1) Write HPIC 0x00000000.

(2) Write HPIA 0x80001234 (The example in reference guide).

(3) Write HPID 0x1234abcd.

(4) Read HPIC. In the debug window of CCS for MSP430, the value is 0x00080008.

(5) Read HPIA. In the debug window of CCS for MSP430, the value is 0x80001234.

(6) Read HPID. In the debug window of CCS for MSP430, the value is 0x1234abcd.

(7) Write HPIC 0x00000002. In the debug window of CCS for DSP, the program can enter the interrupt function of DSPINT and I can read the value change of HPIC from the Registers window.

From the previous steps, I think I have verified that I can access (write/read) the HPIC, HPIA and HPID successfully. In the DSP, I set a pointer to the address 0x80001234 in the main function.

int *ram_test = (int *)0x80001234;

*ram_test = 0; //Initialization

Then the DSP will run in a while loop. The DSP can be interrupted by DSPINT. However, *ram_test always equals 0 in the Expressions window . Would you please help me solve this problem?

BTW, the connection between MSP430 and 6713 DSK is

HAS->3.3V VCC, HDS2->3.3v VCC, HCS->GND, HDS1->P1.6, HCNTL1->P1.5, HCNTL0->P1.4, HHWIL->P1.3

HRW->P1.2, HINT->P4.3, HRDY->P4.0.

HD7-HD0->P3.7-P3.0, HD15-HD10,->P2.7-P2.2, HD9->P8,2, HD8->P2.0

Thanks

Bing

 

  • 0
    TI__Guru** 116100 points

    Hi,

    To interrupt the CPU, the host must:

    1. Drive both UHPI_HCNTL1 and UHPI_HCNTL0 low to request a write to HPIC.
    2. Write 1 to the DSPINT bit in HPIC.


    When the host sets the DSPINT bit, the HPI generates an interrupt pulse to the CPU. If this maskable
    interrupt is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine
    (ISR).


    Before the host can use DSPINT to generate a subsequent interrupt to the CPU, the CPU must
    acknowledge the current interrupt by writing a 1 to the DSPINT bit. When the CPU writes 1, DSPINT is
    forced to 0. The host should verify that DSPINT = 0 before generating subsequent interrupts. While
    DSPINT = 1, host writes to the DSPINT bit do not generate an interrupt pulse.
    Writes of 0 have no effect. A hardware reset immediately clears DSPINT and thus clears an active
    host-to-CPU interrupt.

  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 20 points

    Hello Stalin,

    Thanks for your reply. But I think this is not my problem. I can use MSP430 to interrupt DSP successfully and I can read the value of HPIC in the debug window of CCS for DSP. My problem is after I write HPIA and HPID, the DSP cannot update the value of memory according to HPIA and HPID.

    Thanks,

    Bing

  • 0 in reply to Bing Han1
    TI__Guru** 116100 points

    Hi Bing,

    Note that the addresses loaded into the HPI address registers can be configured by the HPIBYTEAD bit in
    the chip configuration 1 register (CFGCHIP1) of the system configuration module. If byte address is
    selected (HPIBYTEAD = 1), the address must be 32-bit word aligned (with the least-significant two bits
    equal to zero).

    According to the TRM, Have you configured CFGCHIP register for HPIBYTEID?

  • 0 in reply to Titusrathinaraj Stalin
    TI__Guru*** 125430 points

    A couple other possibilities:

    1. You should use "volatile" for your pointer definition so the compiler knows it can't perform any optimizations and reduce the number of reads.
    2. Check your cache configuration.  If the MAR bits for that region are enabled to make the external memory cacheable, then you would need to explicitly perform a cache-invalidate of that block of memory before each read.