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Sw Implementation of RIO Message Passing

MattB
Expert 2025 points

Hi,

Is it possible/reasonable to implement the RIO Message Passing logical layer in software?

We have a C6455 connected to an OMAPL-137 via SRIO and an FPGA. The C6455 is connected to the FPGA with SRIO; we expect to stream video from the FPGA to the C6455. We are using the Altera RIO MegaCore to implement SRIO in the FPGA. The FPGA is also connected to an OMAPL-137 and we need to send control data from the C6747, over the EMIF to the FPGA and on to the C6455 via the SRIO.

I had thought we could send SRIO Messages from the C6747 but it has just become clear to me that the FPGA MegaCore doesn't implement the RIO Message Passing logical layer. It does implement the Direct I/O logical layer so streaming the video is easy.

Is a device like the C6747 capable of running a RIO Message Passing implementation and if so is it something that could be implemented with a reasonable amount of effort?

Are there any example software RIO Message Passing implementations available anywhere?

Are there any tools/libraries from 3rd party vendors that might help me? Obviously a 3rd-party library would have to capable of talking to the FPGA Physical Layer over the C6747 EMIF.

Does any of what I've written make sense?

Thanks,

Matt

  • 0
    TI__Mastermind 41665 points

    MattB said:
    Is it possible/reasonable to implement the RIO Message Passing logical layer in software?

    I think this really depends on how the SRIO implementation in the FPGA works, if it lets you control the bit stream directly I see no reason that you could not generate the required message bit streams in software.

    MattB said:
    Is a device like the C6747 capable of running a RIO Message Passing implementation and if so is it something that could be implemented with a reasonable amount of effort?

    It seems like it would be able to, I took a quick look at the messaging protocol from the SRIO spec and it looks like it should be feasible assuming the FPGA implementation gives you the access you need, it looks far simpler than a TCP/IP networking implementation and that is something that has existed for the C6x DSPs for a long time. How much effort it would take is hard to say as it depends on so many variables and what is considered reasonable.

    MattB said:

    Are there any example software RIO Message Passing implementations available anywhere?

    Are there any tools/libraries from 3rd party vendors that might help me? Obviously a 3rd-party library would have to capable of talking to the FPGA Physical Layer over the C6747 EMIF.

    Not that I am aware of,  but I do not do much work with SRIO, and when I did it was only with the hardware SRIO peripheral in the C6455, I would probably start by asking Altera if they have any suggestions for message passing with their RIO IP core. I would not be surprised to find something out there, perhaps someone else on the forum can comment on this angle.

  • 0 in reply to Bernie Thompson TI
    Guru 10385 points

    Hi Matt/Bernie

    The presentation by Travis S. that Matt posted in another forum discussion (thanks Matt)

    http://learningmedia.ti.com/public/c6474/C64x_SRIO/C6474_SRIO.pdf

    http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11392/44292.aspx#44292

    made me think that the protocol was already handled by the CPPI. But after more reading, I think the CPPI only handles link listing of packets for a  transfer that is greater than 256 bytes. Am I understanding this correctly?

    Why would you need the message passing protocol (Part II)? The only difference I see is the use of absolute target addresses for Part I Input/Output whereas Part II Message Passing Protocol allows the use of mailboxes thereby giving more destination flexibility. Are there other reasons?

    Both Part I and Part II allow simultaneous transactions.

    I have a C6474 evm and TI has a direct IO example. Unfortunately do not have a Rapid IO Specification Part II Message Passing example. That would have been incredibly helpful.

    Am I correct in concluding that TI has implemented Part I Input/Output Specification and a protocol stack is required to implement the Part II Message Passing Protocol?

    Cheers

  • 0 in reply to Eddie3909
    Expert 2025 points

    Hi Eddie,

    Hopefully someone who knows what they are talking about will reply but here's what I think...

    Eddie said:
    the protocol was already handled by the CPPI

    On the C6455 messaging passing is supported by the SRIO peripheral, in particular the CPPI.

    Eddie said:
    But after more reading, I think the CPPI only handles link listing of packets for a  transfer that is greater than 256 bytes.

    spru976c.pdf section 2.3.4.1 describes the RX buffer descriptor field and says the payload can be from 1 to 512 double words. I believe that the C6455 CPPI will sort out messages that span multiple packets. In other words, 256 bytes is the maximum physical layer packet size but SRIO and the C6455 support messages spanning multiple packets.

    Eddie said:
    Why would you need the message passing protocol (Part II)?

    Message passing helps to support systems where the processing elements don't know about each others memory maps.

    Eddie said:
    Are there other reasons?

    I thought Message Passing matched my problem domain nicely. In other words, I want to pass messages between DSPs and thought I would use Message Passing. The RapidIO MQT also fitted nicely with this problem.

    But then I realised that while the C6455 supports Message Passing the other processor (C6747 and FPGA) doesn't. So I briefly considering writing something in software to do Message Passing on the C6747.

    Obviously this is a simple system created by a single vendor (me) so we do understand the memory maps of all processing elements and hence Messaging Passing is not necessary. We can use SRIO Direct I/O to send data between the C6455 and the FPGA/C6747, that's fine and we've almost got it working at the very basic level.

    What I think I need to do now is make a DSP/BIOS MSGQ Transport layer for SRIO Direct I/O but I'm a bit worried that this will not be trivial! I guess this is the subject of another thread.

    Thanks,

    Matt