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Audiocodec(TLV320AIC3254) issues when interfaced to OMAP4460



Hi All,

this cont.. of post

http://e2e.ti.com/support/omap/f/849/p/321248/1140883.aspx#1140883

                         Now we routing audio directly to HPL and HPR.  We are able to probe all the clocks properly i.e  MCLK 25MHz, BCLK  396kHz and WCLK 12KHz. Also we are able to hear noise at HPL and HPR. attached is the boot log, register setting file for your reference. pls share your opinion on this.

Also when we configure the codec as master we are not seeing the clocks on the o/ps

[ 145.860290] DRR2: 0x34444612
[ 145.868133] DRR1: 0x0000
145.871002] DXR2: 0x0000
145.873779] DXR1: 0x0000
145.876739] SPCR2: 0x0000
145.879577] SPCR1: 0x0000
145.882415] RCR2: 0x0000
145.885314] RCR1: 0x0000
145.888122] XCR2: 0x0000
145.890899] XCR1: 0x0000
145.893829] SRGR2: 0x2000
145.896606] SRGR1: 0x0001
145.899383] PCR0: 0x0000
145.902313] ***********************
145.907226] UT Codec debug: IFACE1 reg 0
145.911743] UT Codec debug: IFACE2 reg 0
145.916198] UT Codec debug: IFACE3 reg 0
145.920684] UT Codec debug: CLKMUX reg 3
145.931427] UT: Codec registers in hw params
145.936248] IFACE1 = 0
145.939056] NDAC = 88
145.941680] MDAC = 82
145.944396] PWRCFG = 8
145.947235] LDOCTL = 0
145.950073] DACSETUP = d6
145.953033] DACMUTE = 0
145.955810] **** McBSP2 regs ****
145.959350] DRR2: 0x34444612
145.962615] DRR1: 0x0000
145.965423] DXR2: 0x0000
145.968200] DXR1: 0x0000
145.971130] SPCR2: 0x0230
145.973907] SPCR1: 0x0030
145.976715] RCR2: 0x8041
145.979614] RCR1: 0x0040
145.982391] XCR2: 0x8041
145.985198] XCR1: 0x0040
145.988098] SRGR2: 0x1022
145.990905] SRGR1: 0x103d
145.993774] PCR0: 0x0f0f
145.996582] ***********************

6201.Bootlog_12Mar_10pm.pdf

2843.tlv320aic32x4.c

Regards,

Raghunath