Cache / Memory AM3359

Daniel L

Intellectual 775 points

Other Parts Discussed in Thread: SYSBIOS

Hello,

i am using the ICE Board with IND SDK1.1.0.1 and SysBios.

My application (based on the ethercat example) includes the SPI with EDMA.

The question regarding the memory/cache is:

1. Is it possible to "bypass" the cache, that the memcpy() function directly access the EDMA-TX-RX-buffers in memory (which is also accessed by the EDMA), without using the function CacheDataInvalidateBuff() ? Something like a "Write through" configuration?

2. I think the latency will not change (Am i right ?), when i not use the cache for the buffers, because the function CacheDataInvalidateBuff() admits a directly access to memory.

Regards,

Daniel

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Moving this to the SYS/BIOS forum.

0 PratheeshGangadhar over 12 years ago

TI__Guru 50721 points

Hi,

Are you referring to DDR by memory ? If yes, you can configure any 1MB block as uncached via MMU config and allocate EDMA buffers from here. No need to take care of cache coherency in this case. But of course there is a penalty accessing this memory directly using CPU/A8 as its uncached.

For (2), I believe this really depends on how often CPU access this memory for processing post EDMA transfer.

0 Daniel L over 12 years ago in reply to PratheeshGangadhar

Intellectual 775 points

Yes DDR.

So you mean something like this:

SYS_MMU_ENTRY applMmuEntries[] = {
     {(void*)0x08200000,0}, 
     {(void*)0xFFFFFFFF,0xFFFFFFFF}  
}

Now there would be a memory section of 1 MB which is not cacheable,shareable,bufferable. Is this the correct configuration?? Which is the right way to allocate the EDMA buffers with start from this section (0x82000000) ?

What do you mean with with penalty accessing this memory direclty?

The CPU should be able to access the DDR directly, like the EDMA it does.

0 PratheeshGangadhar over 12 years ago in reply to Daniel L

TI__Guru 50721 points

Yes, correct. There was a typo above

SYS_MMU_ENTRY applMmuEntries[] = {
     {(void*)0x82000000,0}, 
     {(void*)0xFFFFFFFF,0xFFFFFFFF}  
}

You can use linker command file and data section pragma to force variables to a section. This may not be the only way though.

#pragma DATA_SECTION ( symbol , " section_name ");

In linker.cmd file
section_name > 0x82000000

For CPU to read data from L1 cache to register file takes ~ 1 cycle, L2 cache it takes ~ 12 cycles and from DDR ~ 60 or more cycles.

No issues with CPU  accessing DDR directly, just that its way too slower when DDR is uncached, so you might want to do necessary benchmarking 
to make sure that this latency is fine for your application.

0 Daniel L over 12 years ago in reply to PratheeshGangadhar

Intellectual 775 points

Ok.
I am not familiar with the linker command file and pragma statements.
Can you give me a little bit more input? Or an example how i do this?

0 PratheeshGangadhar over 12 years ago in reply to Daniel L

TI__Guru 50721 points

You can use linker command file and data section pragma to force variables to a section. This may not be the only way though.

#pragma DATA_SECTION ( symbol , "section_name");

In linker.cmd file

section_name > 0x82000000

Eg:-

#pragma DATA_SECTION ( txbuf , "sect_dma_buf");

Uint8 txbuf[512];

#pragma DATA_SECTION ( rxbuf , "sect_dma_buf");

Uint8 rxbuf[512];

In the linker.cmd file of your project (eg:- sdk\protocols\ethercat_slave\ecat_appl\am335x.cmd) specify following within SECTIONS directive

sect_dma_buf > 0x82000000

Looks like my previous post was garbled - so pasting rest of the info here

For CPU to read data from L1 cache to register file takes ~ 1 cycle, L2 cache it takes ~ 12 cycles and from DDR ~ 60 or more cycles.

No issues with CPU accessing DDR directly, just that its way too slower when DDR is uncached, so you might want to do necessary benchmarking to make sure that this latency is fine for your application.

Processors

Processors forum

Cache / Memory AM3359