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UART registers access problems

Marco Destro
Intellectual 590 points

Other Parts Discussed in Thread: AM3359

Hi all,

I'm using the AM3359 on BB Black platform.

I have noticed a strange issue on UARTx behaviour. From the shell prompt, if I type

devmem2 0x4802400

the system give back

/dev/mem opened.
Memory mapped at address 0xb6f16000.
Bus error

It happens for all the uarts (1,2,3,4,5) except for the uart 0. In that case

root@beaglebone:~ > devmem2 0x44E09000
/dev/mem opened.
Memory mapped at address 0xb6f6c000.
Read at address  0x44E09000 (0xb6f6c000): 0x00000000

I can't figure out the reason of this behaviour.

Another question involves the way that the UART registers are mapped on memory . From MPU TRM rev J , the pages 171,172,173 show the memory mapping of the UART peripherals. In particular , UART0 UART1 UART2.

The highlighted link all leads to page 4018 , paragraph 19.5. 

Looking at the table 19-29 i notice something strange to me.

It seems that different registers are mapped on the same offesets ... is that right?  I guess I'm missing something

But ... how do you explain this?!

In the end, what is the best way to set this registers?! My goal is to setup the DMA for the UART

Any help is highly appreciated

Thanks In advance

marco

  • 0
    TI__Expert 5960 points

    Hi Marco,

    Please take a look at chapter 8 of the AM335x TRM. You need to enable the clock to the specific peripheral to be able to access the registers.  For example, see 8.1.12 Clock Module Registers and for Uart1, see 8.1.12.1.21 CM_PER_UART1_CLKCTRL Register (offset = 6Ch) [reset = 30000h].

  • 0 in reply to Jeff L
    Intellectual 590 points

    Thanks A lot Jeff :)

    Bus error problem perfectly solved. 

    It remains only the problem of figuring out the right offset from page 4018.
    Then I will focus on enabling DMA for the tx and rx fifo.