timing model for the DDR memory controller which is inside the DM8148

Kwan,

Timing models and signal integrity models are different.

If you are concerned about signal integrity then you need to use IBIS models (used by Hyperlynx).

IBIS models do not contain timing information to allow checking of signal to signal relationships.

Verilog/VHDL timing models are only useful for digital timing verification and do not contain any signal integrity information. These are also not necessary and all the timing parameters for IO signals are quoted in the datasheet. The timing information is a range (min-max) to account for variations in temperature, voltage, power supply etc...) Verilog/VHDL models do not usually contain these variations since they are much more discrete models.

The timing of the DDR is JEDEC compliant and as long as you follow all the JEDEC and TI design rules for length matching and impedance control then the timings will be correct. You should probably still do signal integrity simulations if you can but you will use IBIS models for these simulations.

BR,

Steve

Hi Steve

Understand the IBIS Model is the primary requirement for SI Simulation. IBIS models are used to model the various signal I/O characteristics for the memory controller and DDR devices.

But for SI analysis of the DDR bus, the HyperLynx uses the DDR Wizard for which one of the requirement is the timing model of the DDR Controller. I also had a look at the datasheet as well as the TRM but could not extrapolate the values for the parameters required by the timing model.

The parameters which I am looking for are tCKAC (pre-launch delay, CK to Address and Command signals), tCKCTL(pre-launch delay, CK to Control signals), tCKDQS(Output delay or skew, CK output to DQS output), tDQSDQ(pre-launch delay, DQS output to DQ and DM outputs) and tDQDQS(Tolerable input skew between DQS and DQ).

It would be very helpful if you or someone can help deduce one of the parameters listed above and hopefully I get the drift for the rest. I can attach the waveform representation of these parameters if required. Thanks in advance!

Regards,

KS Padmanabhan

Just to reiterate, all above parameters have minimum and maximum values as rightly pointed out by Steve. Also, the application processor we are using is DM8148.

Regards.

KS Padmanabhan

Unfortunately the DDR wizard makes many assumptions and is incompatible with many different IBIS model formats.

For example the wizard requires that the data and other IO models are modeled as IO and cannot handle discrete selectors with separate input and output models. This is a major issue since TI generally includes separate input and output models rather than IO models.

It also assumes the model to model relative timing is accurate, but this is not a general requirement for IBIS since IBIS is only designed really for signal integrity and not pin to pin timing checks.

The bottom line really is that the DDR wizard is not really ready for prime time at the moment I don't think, and TI does not plan to provide models which are compatible with the wizard requirements.

The TI DDR PHY is JEDEC compliant from a timing perspective and IBIS models can be used to validate your board design signal integrity. We provide design support tools to validate signal to signal margin/skew etc..., but these really only validate that you are following the JEDEC rules.

BR,

Steve

Thanks, Steve for highlighting possible limitations while using these IBIS models with HyperLynx and its DDR Wizard.

I would still be interested if we can have atleast  waveforms and timing information with respect to the DDR2/3 controller of 8148. I am unable to find it in the datasheet, which mainly seems to focus on layout/routing recommendations for the DDRx interface and has very little information on the Electrical/timing information. Is it available only under NDA? 

One more thing which i came across in the web - JEDEC spec is targeted only for DDR devices and DDR controller spec is outside it purview. Is this true? In that case, there might already be a need for the detailing timing diagram/parameters for our design validation?

Regards,

KS

KS,

TI does not provide DDR3 timing for these devices.  This is beyond our support model.  Our support model is limited to layout guidelines and software tools.  Also, the answer does not change with an NDA in place.

Tom

Tom

There is a requirement for us to validate the DDR interface and we need the timing information of the DDR controller to complete this. There is no way for us to ensure this without the timing information. Is there any way at all we can get this info?

I am not sure why TI cannot support its customers with the timing information of the DDR controller. Can you mention how can we go about validating the design without the complete electrical spec of the interface?  We have used many TI chips in the past and continue to use them presently. This is the first time we are encountering such a gap in information flow.

Regards,

KS

KS,

What interface and device did you previously use?  We have this consistent support model across several business units in out Processors Division.  We do not provide timing information for DDR2.  Our support is limited to layout guidelines along with recommended topologies.  We did not embrace tools like HyperLinx for this since they are often misleading.  It is understood that those tools are getting better but this is the support methodology established for DDR2 memory interfaces.

Tom

Tom,

I was just referring to timing information for interfaces in general and not DDR interfacing timing. Also, the first time we are doing SI simulation and hence the need for timing model. 

Regards,

KS

KS,

SI simulations are all about signal integrity and not about timing.

Timing information needs to be validated from the datasheet timing parameters provided.

DDR is slightly different in this manner since it is governed by the JEDEC standard. All other IOs which are not governed by their appropriate standards will have max/min timing parameters listed in the datasheet. These should be used in conjunction with the other peripheral datasheets to ensure all setup and hold parameters are met.

IBIS models and signal simulations then should be used to verify the integrity of each critical signal.

IBIS models do not contain timing information so cannot be used for timing validation. IBIS models are only useful for simulating individual signals, one at a time, and cannot be used to check pin to pin timings.

BR,

Steve

Steve

I agree with you that SI is all about that - integrity (or we say quality for a closer word) of the signal. SI simulations is just an indicator of how good/bad the signals in our board's net are.

But this timing thing comes into picture with the DDR Wizard which is in-built with HyperLynx. Its useful for the SI analysis of the whole DDR bus and also looks into the timing aspects such as setup/hold time violations of the signals. To do this, there are two things required among other things- timing model of DRAM device and timing model of Memory controller. The former is standardized by JEDEC and all devices have same timing-related info while the latter is not, which gives rise to slight changes - vendor to vendor. That is the whole reason behind me requesting for timing information of the memory controller.

The tool itself comes with two default timing models - one each for DDR device and the Memory controller. We can use the former straightaway for the DDR device but the latter needs to be tweaked based on the memory controller's timing information for accuracy.

All this info is mostly based on what is available in the web and also with inputs from Mentor who sell HyperLynx. I would be happy to stand corrected and get my understanding right. Please let me know your views.

Regards,

KS

Unfortunately we don't have any additional timing information available and cannot support the Mentor tool.

Our specifications in the datasheet regarding layout, i.e. length matching etc..., are all that is needed to ensure correct timing can be achieved.

Once your hardware is available there is a utility which needs to be run on the hardware to measure the PCB characteristics and then generate timing information which then needs to be programmed to the memory controller.

You can find more details about this procedure here...

http://processors.wiki.ti.com/index.php/DM816x_Design_Resources

You will also find a spreadsheet which should be used to ensure you are compliant with the datasheet requirements.

BR,

Steve