1.First question：
Core0 send the same msg to core1-7；core1-7 receive the msg ，after core1-7 do their task，core1-7 send the msg to core 0；but core0 can not get the msg from core1-7，it is successful。
When i make a loop in the code，it can loop two times，then it error：
ti.sdo.ipc.MessageQ: line 257: assertion failure: A_heapIdInvalid: heapId is invalid
xdc.runtime.Error.raise: terminating execution
the code is :
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* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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#include<stdio.h>
#include <xdc/std.h>
#include <xdc/cfg/global.h>
/* XDC.RUNTIME module Headers */
#include <xdc/runtime/System.h>
#include <xdc/runtime/IHeap.h>
#include <xdc/runtime/Timestamp.h>
/* IPC module Headers */
#include <ti/ipc/MultiProc.h>
#include <ti/ipc/MessageQ.h>
#include <ti/ipc/SharedRegion.h>
/* PDK module Headers */
#include <ti/platform/platform.h>
/* BIOS6 module Headers */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/family/c66/Cache.h>
/* CSL modules */
#include <ti/csl/csl_cacheAux.h>
#include <ti/csl/csl_chip.h>
/* QMSS LLD*/
#include <ti/drv/qmss/qmss_drv.h>
#include <ti/drv/qmss/qmss_firmware.h>
/* CPPI LLD */
#include <ti/drv/cppi/cppi_drv.h>
#include <ti/transport/ipc/examples/common/bench_common.h>
#include <ti/transport/ipc/qmss/transports/TransportQmss.h>
/************************ EXTERN VARIABLES ********************/
/* QMSS device specific configuration */
extern Qmss_GlobalConfigParams qmssGblCfgParams;
/* CPPI device specific configuration */
extern Cppi_GlobalConfigParams cppiGblCfgParams;
/**************************************************************/
#define NUM_MONOLITHIC_DESC numDescriptors
#define SIZE_MONOLITHIC_DESC descriptorSize
#define MONOLITHIC_DESC_DATA_OFFSET 16
#define HEAP_ID 0
/* Number of times to run the loop */
#define NUMLOOPS 100
#define NUMIGNORED (5)
#define NUM_MSGS (10)
/* Benchmark parameters */
Char localQueueName[6];
Char nextQueueName[6];
Char prevQueueName[6];
//Char core_temp[6];
UInt numCores = 0;
UInt16 prevCoreId;
UInt16 selfId;
UInt64 timeAdj = 0;
Types_FreqHz timerFreq, cpuFreq;
/* Results */
UInt32 rawtimestamps[NUMLOOPS];
UInt32 latencies[NUMLOOPS - 1];
MessageQ_Handle messageQ =NULL;
MessageQ_QueueId prevQueueId;
MessageQ_QueueId nextQueueId,nextQueueId1,nextQueueId2,nextQueueId3,nextQueueId4,nextQueueId4,nextQueueId5,nextQueueId6,nextQueueId7;
UInt64 timeLength = 0;
Float cpuTimerFreqRatio;
Statistics latencyStats;
/* Descriptor pool [Size of descriptor * Number of descriptors] */
/* place this monolithic descritor pool in shared memory */
#pragma DATA_SECTION (monolithicDesc, ".desc");
#pragma DATA_ALIGN (monolithicDesc, 16)
UInt8 monolithicDesc[SIZE_MONOLITHIC_DESC * NUM_MONOLITHIC_DESC];
#define NUM_MSGS_TO_PREALLOC (8000)
#pragma DATA_SECTION (txMsgPtrs, ".msgQ_ptrs");
TstMsg *txMsgPtrs[NUM_MSGS_TO_PREALLOC];
#pragma DATA_SECTION (rxMsgPtrs, ".msgQ_ptrs");
TstMsg *rxMsgPtrs[NUM_MSGS_TO_PREALLOC];
/**
* @b Description
* @n
* This functions prints the statistics gathered for the transport during
* the latency test.
*/
void convertyuv422torgb565( unsigned char inbuf[],unsigned char outbuf[],int width,int height)
{
int rows,cols;
int y,u,v,r,g,b,rdif,invgdif,bdif;
int YPOS,UPOS,VPOS;
YPOS=0;
UPOS=1;
VPOS=3;
for(rows=0;rows<height;rows++)
{
for(cols=0;cols<width;cols++)
{
y = inbuf[YPOS+cols*2+rows*1920*2];
if(cols%2==0)
{
u = inbuf[UPOS+cols*2+rows*1920*2] - 128;
v = inbuf[VPOS+cols*2+rows*1920*2] - 128;
}else{
u = inbuf[UPOS+(cols-1)*2+rows*1920*2] - 128;
v = inbuf[VPOS+(cols-1)*2+rows*1920*2] - 128;
}
rdif = v + ((v * 103) >> 8);
invgdif = ((u * 88) >> 8) +((v * 183) >> 8);
bdif = u +( (u*198) >> 8);
r = y + rdif;
g = y - invgdif;
b = y + bdif;
r=r>255?255:(r<0?0:r);
g=g>255?255:(g<0?0:g);
b=b>255?255:(b<0?0:b);
*(outbuf++) =( ((g & 0x1C) << 3) | ( b >> 3) );
*(outbuf++) =( (r & 0xF8) | ( g >> 5) );
}
}
}
/**
* @b Description
* @n
* This function initalizes the platform. It has called at startup. This is defined in the
* .cfg file via the Startup.firstFxns.$add('&initPlatform'); definition.
*/
void initPlatform(void)
{
platform_init_flags pFormFlags;
platform_init_config pFormConfig;
/* Status of the call to initialize the platform */
UInt32 pFormStatus;
/* Only run on single core */
if (CSL_chipReadReg (CSL_CHIP_DNUM) == 0)
{
/*
* You can choose what to initialize on the platform by setting the following
* flags. Things like the DDR, PLL, etc should have been set by the boot loader.
*/
memset( (void *) &pFormFlags, 0, sizeof(platform_init_flags));
memset( (void *) &pFormConfig, 0, sizeof(platform_init_config));
pFormFlags.pll = 0; /* PLLs for clocking */
pFormFlags.ddr = 0; /* External memory */
pFormFlags.tcsl = 1; /* Time stamp counter */
pFormFlags.phy = 0; /* Ethernet */
pFormFlags.ecc = 0; /* Memory ECC */
pFormConfig.pllm = 0; /* Use libraries default clock divisor */
pFormStatus = platform_init(&pFormFlags, &pFormConfig);
/* If we initialized the platform okay */
if (pFormStatus != Platform_EOK)
{
/* Initialization of the platform failed. */
System_printf("Platform failed to initialize. Error code %d \n", pFormStatus);
}
}
}
void convert_func(){
Int status;
int i;
//UInt numReceived;
MessageQ_Msg msg;
UInt64 timeStamp=0;
UInt64 timeAdj=0;
double throughPut;
if (selfId == 0) {
System_printf("tsk0. selfproc=%d nextQueueName (%s) openned, nextQueueId=%d-%d-%d-%d-%d-%d-%d\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE1-7", nextQueueId1,nextQueueId2,nextQueueId3,nextQueueId3,nextQueueId4,nextQueueId5,nextQueueId6,nextQueueId7);
msg= MessageQ_alloc(HEAP_ID, MESSAGE_SIZE_IN_BYTES);
if (msg== NULL) {
System_abort("MessageQ_alloc failed\n");
}
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE1-7", msg);
status = MessageQ_put(nextQueueId1, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId2, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId3, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId4, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId5, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId6, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
} status = MessageQ_put(nextQueueId7, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
System_printf("core 0 MessageQ_put done\n");
System_printf("convert start\n");
/* Take time at start of test */
timeStamp = getStartTime64();
convertyuv422torgb565( (uint8_t *)0x90000000,(uint8_t *)0x91000000,1920,1080/8);
for(i=1;i<=7;i++){
status = MessageQ_get(messageQ, &msg, MessageQ_FOREVER);
if (status < 0) {
System_abort("MessageQ_get failed\n");
}
//System_printf("MessageQ_get %d time\n",i);
}
//System_printf("convert done\n");
/* Get execution time to transfer all messages */
timeLength = getExecutionTime64(timeStamp, timeAdj);
throughPut = (double)CYCLES_TO_US(timeLength, 1000000000);
System_printf("covert time is %f us\n",throughPut);
//��DDR 91000000����ʼ����ת����rgb����
// FILE *fp2;
// fp2=fopen("conpspyzj.rgb","ab");
// fwrite((void *)0x91000000, 1, 720*480*2, fp2);
// fclose(fp2);
MessageQ_free(msg);
}
if(1<=selfId <= 7){
//System_printf("tsk0. selfproc=%d nextQueueName (%s) openned, nextQueueId=%d\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE0", nextQueueId);
//System_printf("core %d call MessageQ_get",selfId);
status = MessageQ_get(messageQ, &msg, MessageQ_FOREVER);
if (status < 0) {
System_abort("MessageQ_get failed\n");
}
convertyuv422torgb565( (uint8_t *)(0x90000000+(1920*1080/4)*selfId),(uint8_t *)(0x91000000+(1920*1080/4)*selfId),1920,1080/8);
//System_printf("core %d call MessageQ_put\n ",selfId);
status = MessageQ_put(nextQueueId, msg);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
}
}
/**
* @b Description
* @n
* This configures the descriptor region and initializes CPPI, and QMSS.
* This function should only be called once per chip.
*
* @retval
* Success - 0
* @retval
* Error - <0
*/
Int32 systemInit (Void)
{
Qmss_InitCfg qmssInitConfig; /* QMSS configuration */
Qmss_MemRegInfo memInfo; /* Memory region configuration information */
Qmss_Result result;
UInt32 coreNum;
coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
System_printf ("\n-----------------------Initializing---------------------------\n");
System_printf ("Core %d : L1D cache size %d. L2 cache size %d.\n", coreNum, CACHE_getL1DSize(), CACHE_getL2Size());
memset ((Void *) &qmssInitConfig, 0, sizeof (Qmss_InitCfg));
/* Set up the linking RAM. Use the internal Linking RAM.
* LLD will configure the internal linking RAM address and maximum internal linking RAM size if
* a value of zero is specified.
* Linking RAM1 is not used */
qmssInitConfig.linkingRAM0Base = 0;
qmssInitConfig.linkingRAM0Size = 0;
qmssInitConfig.linkingRAM1Base = 0;
qmssInitConfig.maxDescNum = NUM_MONOLITHIC_DESC /*+ total of other descriptors here */;
#ifdef xdc_target__bigEndian
qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);
#else
qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);
#endif
/* Initialize Queue Manager SubSystem */ //Qmss_init
result = Qmss_init (&qmssInitConfig, &qmssGblCfgParams);
if (result != QMSS_SOK)
{
System_printf ("Error Core %d : Initializing Queue Manager SubSystem error code : %d\n", coreNum, result);
return -1;
}
//Cppi_init
result = Cppi_init (&cppiGblCfgParams);
if (result != CPPI_SOK)
{
System_printf ("Error Core %d : Initializing CPPI LLD error code : %d\n", coreNum, result);
}
System_printf ("address of monolithicDesc[] = 0x%x. Converted=0x%x\n", monolithicDesc, l2_global_address ((UInt32) monolithicDesc));
/* Setup memory region for monolithic descriptors */
memset ((Void *) &monolithicDesc, 0, SIZE_MONOLITHIC_DESC * NUM_MONOLITHIC_DESC);
memInfo.descBase = (UInt32 *) monolithicDesc; /* descriptor pool is in MSMC */
memInfo.descSize = SIZE_MONOLITHIC_DESC;
memInfo.descNum = NUM_MONOLITHIC_DESC;
memInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
memInfo.memRegion = (Qmss_MemRegion) descriptorMemRegion;
memInfo.startIndex = 0;
result = Qmss_insertMemoryRegion (&memInfo);
if (result < QMSS_SOK)
{
System_printf ("Error Core %d : Inserting memory region %d error code : %d\n", coreNum, memInfo.memRegion, result);
return -1;
}
else
{
System_printf ("Core %d : Memory region %d inserted\n", coreNum, result);
}
/* Writeback the descriptor pool. Writeback all data cache.
* Wait until operation is complete. */
Cache_wb (monolithicDesc,
SIZE_MONOLITHIC_DESC * NUM_MONOLITHIC_DESC,
Cache_Type_ALLD, TRUE);
return 0;
}
/**
* @b Description
* @n
* Task which kicks off the latency and throughput tests
*/
Void tsk0(UArg arg0, UArg arg1)
{
Int status;
Int cnt=10;
System_printf("tsk0 starting\n");
/* Register this heap with MessageQ */
if(selfId==0){
MessageQ_registerHeap((IHeap_Handle)SharedRegion_getHeap(0), HEAP_ID);
/* Open the 'next' remote message queue. Spin until it is ready. */
do {
status = MessageQ_open("CORE1", &nextQueueId1);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE2", &nextQueueId2);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE3", &nextQueueId3);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE4", &nextQueueId4);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE5", &nextQueueId5);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE6", &nextQueueId6);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE7", &nextQueueId7);
Task_yield();
}
while (status < 0);
}
else{
MessageQ_registerHeap((IHeap_Handle)SharedRegion_getHeap(0), HEAP_ID);
do {
status = MessageQ_open("CORE0", &nextQueueId);
Task_yield();
}
while (status < 0);
}
while(cnt--){
convert_func();
System_printf("cnt=%d\n",cnt);
}
detachAll(MultiProc_getNumProcessors());
System_exit(0);
}
/**
* @b Description
* @n
* Main - Initialize the system and start BIOS
*/
Int main(Int argc, Char* argv[])
{
Int32 result = 0;
Types_Timestamp64 time64;
UInt64 timeStamp = 0;
Timestamp_getFreq(&timerFreq); //Get the timestamp timer's frequency (in Hz) ��ʱ��
System_printf("timerFreq.lo = %d. timerFreq.hi = %d\n", timerFreq.lo, timerFreq.hi);
BIOS_getCpuFreq(&cpuFreq); //Get CPU frequency in Hz
System_printf("cpuFreq.lo = %d. cpuFreq.hi = %d\n", cpuFreq.lo, cpuFreq.hi);
cpuTimerFreqRatio = (Float)cpuFreq.lo / (Float)timerFreq.lo; //=1
Timestamp_get64(&time64); //Return a 64-bit timestamp
timeStamp = TIMESTAMP64_TO_UINT64(time64.hi,time64.lo);
timeAdj = TIMESTAMP64_TO_UINT64(time64.hi,time64.lo) - timeStamp; //=0
selfId = CSL_chipReadReg (CSL_CHIP_DNUM);
System_printf("Core (\"%s\") starting\n", MultiProc_getName(selfId));
if (numCores == 0) {
numCores = 8; //MultiProc_getNumProcessors(); Number of processors configured with MultiProc =2
}
if (selfId == 0)
{
/* QMSS, and CPPI system wide initializations are run on
* this core */
result = systemInit(); //systemInit
if (result != 0)
{
System_printf("Error (%d) while initializing QMSS\n", result);
}
// FILE *fp1;
// fp1=fopen("conpsp.yuv","r");
// fread((void *)0x90000000,1,720*480*2,fp1);
// fclose(fp1);
// System_printf("fread done\n");
/* Attach all cores. */
attachAll(numCores);
System_printf("core 0 exec attachAll done\n");
// prevCoreId = "1/2/3/4/5/6/7";
//
System_sprintf(localQueueName, "CORE%d", selfId); //localQueueName��ȫ�ֱ���
// System_sprintf(nextQueueName, "CORE%s","1/2/3/4/5/6/7");
// System_sprintf(prevQueueName, "CORE%s", prevCoreId); //System_sprintf���Ǵ�ӡ����ʹprevQueueNameΪ��CORE%d���ַ���
//
// System_printf("localQueueName=%s. nextQueueName=%s. prevQueueName=%s\n",
// localQueueName, nextQueueName, prevQueueName);
/* Create a message queue. */
messageQ = MessageQ_create(localQueueName, NULL);
if (messageQ== NULL) {
System_abort("MessageQ_create failed\n" );
}
}
else{
/* Attach all cores. */
attachAll(numCores);
prevCoreId = 0;
System_sprintf(localQueueName, "CORE%d", selfId); //localQueueName��ȫ�ֱ���
System_sprintf(nextQueueName, "CORE%d",0);
System_sprintf(prevQueueName, "CORE%d", prevCoreId); //System_sprintf���Ǵ�ӡ����ʹprevQueueNameΪ��CORE%d���ַ���
System_printf("localQueueName=%s. nextQueueName=%s. prevQueueName=%s\n",
localQueueName, nextQueueName, prevQueueName);
/* Create a message queue. */
messageQ = MessageQ_create(localQueueName, NULL);
if (messageQ== NULL) {
System_abort("MessageQ_create failed\n" );
}
}
BIOS_start();
System_printf("done BIOS_start\n");
return (0);
}
the log is:
[C66xx_6] timerFreq.lo = 1000000000. timerFreq.hi = 0
cpuFreq.lo = 1000000000. cpuFreq.hi = 0
Core ("CORE6") starting
[C66xx_7] timerFreq.lo = 1000000000. timerFreq.hi = 0
cpuFreq.lo = 1000000000. cpuFreq.hi = 0
Core ("CORE7") starting
[C66xx_0] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_1] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_2] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_3] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_4] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_5] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_0] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_1] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_2] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_3] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_4] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_5] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_0] Core ("CORE0") starting
[C66xx_1] Core ("CORE1") starting
[C66xx_2] Core ("CORE2") starting
[C66xx_3] Core ("CORE3") starting
[C66xx_4] Core ("CORE4") starting
[C66xx_5] Core ("CORE5") starting
[C66xx_0]
-----------------------Initializing---------------------------
Core 0 : L1D cache size 4. L2 cache size 0.
address of monolithicDesc[] = 0xc100000. Converted=0x1c100000
Core 0 : Memory region 0 inserted
core 0 exec attachAll done
tsk0 starting
[C66xx_1] localQueueName=CORE1. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_2] localQueueName=CORE2. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_3] localQueueName=CORE3. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_4] localQueueName=CORE4. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_5] localQueueName=CORE5. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_6] localQueueName=CORE6. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_7] localQueueName=CORE7. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_1] tsk0 starting
[C66xx_2] tsk0 starting
[C66xx_3] tsk0 starting
[C66xx_4] tsk0 starting
[C66xx_5] tsk0 starting
[C66xx_6] tsk0 starting
[C66xx_7] tsk0 starting
[C66xx_0] tsk0. selfproc=0 nextQueueName (CORE1-7) openned, nextQueueId=65536-131072-196608-196608-262144-327680-393216
tsk0. selfProc=0 calling MessageQ_put(nextQueueName=CORE1-7). msg=0xc040380
core 0 MessageQ_put done
convert start
covert time is 16410.0000 us
//
while(cnt--){
convert_func();
System_printf("cnt=%d\n",cnt);
}
[C66xx_6] timerFreq.lo = 1000000000. timerFreq.hi = 0
cpuFreq.lo = 1000000000. cpuFreq.hi = 0
Core ("CORE6") starting
[C66xx_0] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_1] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_2] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_3] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_7] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_0] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_1] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_2] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_3] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_7] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_0] Core ("CORE0") starting
[C66xx_1] Core ("CORE1") starting
[C66xx_2] Core ("CORE2") starting
[C66xx_3] Core ("CORE3") starting
[C66xx_7] Core ("CORE7") starting
[C66xx_0]
-----------------------Initializing---------------------------
Core 0 : L1D cache size 4. L2 cache size 0.
address of monolithicDesc[] = 0xc100000. Converted=0x1c100000
Core 0 : Memory region 0 inserted
[C66xx_4] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_5] timerFreq.lo = 1000000000. timerFreq.hi = 0
[C66xx_4] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_5] cpuFreq.lo = 1000000000. cpuFreq.hi = 0
[C66xx_4] Core ("CORE4") starting
[C66xx_5] Core ("CORE5") starting
localQueueName=CORE5. nextQueueName=CORE0. prevQueueName=CORE0
tsk0 starting
[C66xx_0] core 0 exec attachAll done
[C66xx_1] localQueueName=CORE1. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_2] localQueueName=CORE2. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_3] localQueueName=CORE3. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_4] localQueueName=CORE4. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_6] localQueueName=CORE6. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_7] localQueueName=CORE7. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_0] tsk0 starting
[C66xx_1] tsk0 starting
[C66xx_2] tsk0 starting
[C66xx_3] tsk0 starting
[C66xx_4] tsk0 starting
[C66xx_6] tsk0 starting
[C66xx_7] tsk0 starting
[C66xx_0] tsk0. selfproc=0 nextQueueName (CORE1-7) openned, nextQueueId=65536-131072-196608-196608-262144-327680-393216
tsk0. selfProc=0 calling MessageQ_put(nextQueueName=CORE1-7). msg=0xc040380
core 0 MessageQ_put done
convert start
covert time is 16410.0000 us
[C66xx_1] cnt=9
[C66xx_2] cnt=9
[C66xx_3] cnt=9
[C66xx_4] cnt=9
[C66xx_5] cnt=9
[C66xx_6] cnt=9
[C66xx_7] cnt=9
[C66xx_0] cnt=9
tsk0. selfproc=0 nextQueueName (CORE1-7) openned, nextQueueId=65536-131072-196608-196608-262144-327680-393216
tsk0. selfProc=0 calling MessageQ_put(nextQueueName=CORE1-7). msg=0xc040380
core 0 MessageQ_put done
convert start
[C66xx_1] cnt=8
[C66xx_2] cnt=8
[C66xx_3] cnt=8
[C66xx_4] cnt=8
[C66xx_5] cnt=8
[C66xx_6] cnt=8
[C66xx_7] cnt=8
[C66xx_0] covert time is 16411.0000 us
ti.sdo.ipc.MessageQ: line 257: assertion failure: A_heapIdInvalid: heapId is invalid
xdc.runtime.Error.raise: terminating execution
2.Second question：
But when i add the pcie interrupt context，it is not successful。
Core0 send the same msg to core1-7；core1-7 receive the msg ，after core1-7 do their task，core1-7 send the msg to core 0；but core0 can not get the msg from core1-7，core0 status is idle.why？
the code is:
/* --COPYRIGHT--,BSD
* Copyright (c) 2011, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include<stdio.h>
#include <xdc/std.h>
#include <xdc/cfg/global.h>
/* XDC.RUNTIME module Headers */
#include <xdc/runtime/System.h>
#include <xdc/runtime/IHeap.h>
#include <xdc/runtime/Timestamp.h>
/* IPC module Headers */
#include <ti/ipc/MultiProc.h>
#include <ti/ipc/MessageQ.h>
#include <ti/ipc/SharedRegion.h>
/* PDK module Headers */
#include <ti/platform/platform.h>
/* BIOS6 module Headers */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/family/c66/Cache.h>
/* CSL modules */
#include <ti/csl/csl_cacheAux.h>
#include <ti/csl/csl_chip.h>
/* QMSS LLD*/
#include <ti/drv/qmss/qmss_drv.h>
#include <ti/drv/qmss/qmss_firmware.h>
/* CPPI LLD */
#include <ti/drv/cppi/cppi_drv.h>
#include <ti/transport/ipc/examples/common/bench_common.h>
#include <ti/transport/ipc/qmss/transports/TransportQmss.h>
#define uint32 unsigned int
#define int32 int
#define PCIEXpress_Legacy_INTA 50
#define PCIE_IRQ_EOI 0x21800050
#define PCIE_EP_IRQ_SET 0x21800064
#define PCIE_LEGACY_A_IRQ_STATUS 0x21800184
#define INTC0_OUT3 63
#define BOOT_MAGIC_ADDRESS 0x87FFFC // for C6678
#define BOOT_ENTRY_ADDRESS 0x800000
#define IPC_INTERRUPT_CORE0 0x02620240
#define IPC_INTERRUPT_CORE1 0x02620244
#define IPC_INTERRUPT_CORE2 0x02620248
#define IPC_INTERRUPT_CORE3 0x0262024c
#define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
#define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
/* undocumented register in data manual
* Bit 0 of this register is supposed to give the status of PCIe PLL lock*/
#define PCIE_STS_REG 0x262015C
/* Workaround for PCIe boot mode support for C6678/C6670 */
/* This is a temporary workaround should be removed once fixed in RBL */
/* PCIe Config register base on C6678/C6670 */
#define PCIE_BASE_ADDR 0x21800000
/* PCIe Application registers */
#define PCIE_APP_CMD_STATUS 0x4
#define PCIE_APP_OB_SIZE 0x30
#define PCIE_APP_SERDES_CFG0 0x390
#define PCIE_APP_SERDES_CFG1 0x394
/* PCIe Local Configuration registers */
#define PCIE_VENDER_DEVICE_ID 0x1000
#define PCIE_STATUS_CMD 0x1004
#define PCIE_CLASSCODE_REVID 0x1008
#define PCIE_BAR0 0x1010
#define PCIE_BAR1 0x1014
#define PCIE_BAR2 0x1018
#define PCIE_BAR3 0x101c
#define PCIE_DEVICE_CAP 0x1074
#define PCIE_DEV_STAT_CTRL 0x1078
#define PCIE_LINK_STAT_CTRL 0x1080
#define PCIE_ACCR 0x1118
#define PCIE_DEBUG0 0x1728
#define PCIE_PL_GEN2 0x180C
#define LEGACY_A_IRQ_STATUS_RAW 0x21800180
/* SERDES Configuration registers */
#define PCIE_SERDES_CFG_PLL 0x2620358
int32 devicePowerPeriph (int32 modNum)
{
int32 ret;
/* If the input value is < 0 there is nothing to power up */
if (modNum < 0)
return (0);
if (modNum >= 30)
return (-1);
/* Note that if the sgmii power enable is requested the PA must be
* powered up first */
if (modNum == 8) {
ret = (int32)pscEnableModule (7);
if (ret != 0)
return (ret);
}
return ((int32)pscEnableModule(modNum));
}
void iblPCIeWorkaround()
{
uint32 i;
/* Power up PCIe */
devicePowerPeriph (10);
for(i=0; i<1000; i++) asm (" NOP");
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG0), 0x00062320); /* ss clock */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG1), 0x00022320); /* ss clock */
/* Wait for PCIe PLL lock */
while(!(DEVICE_REG32_R(PCIE_STS_REG) & 1));
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_CLASSCODE_REVID), 0x04800001); /* class 0x04, sub-class 0x80, Prog I/F 0x00, Other multimedia device */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_LINK_STAT_CTRL), 0x10110080); /* extended sync, slot_clk_cfg = 1 */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_VENDER_DEVICE_ID), 0xb005104c); /* Vendor and Device ID */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_DEVICE_CAP), 0x288701); /* L0 = 4, L1 = 3 */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_OB_SIZE), 0x00000003); /* OB_SIZE = 8M */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_PL_GEN2), 0x0000000F); /* num_fts = 0xF*/
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0020); /* Set dbi_cs2 to allow access to the BAR registers */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0x00000FFF); /* 4K */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR1), 0x0007FFFF); /* 512K */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR2), 0x003FFFFF); /* 4M */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR3), 0x00FFFFFF); /* 16M */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0); /* dbi_cs2=0 */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_STATUS_CMD), 0x00100146); /* ENABLE mem access */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_DEV_STAT_CTRL), 0x0000281F); /* Error control */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_ACCR), 0x000001E0); /* Error control */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0); /* non-prefetch, 32-bit, mem bar */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0000007); /* enable LTSSM, IN, OB */
while((DEVICE_REG32_R(PCIE_BASE_ADDR + PCIE_DEBUG0) & 0x11)!=0x11); /* Wait for training to complete */
/* Will never reach here */
return;
}
/************************ EXTERN VARIABLES ********************/
/* QMSS device specific configuration */
extern Qmss_GlobalConfigParams qmssGblCfgParams;
/* CPPI device specific configuration */
extern Cppi_GlobalConfigParams cppiGblCfgParams;
/**************************************************************/
#define NUM_MONOLITHIC_DESC numDescriptors
#define SIZE_MONOLITHIC_DESC descriptorSize
#define MONOLITHIC_DESC_DATA_OFFSET 16
#define HEAP_ID 0
/* Number of times to run the loop */
#define NUMLOOPS 100
#define NUMIGNORED (5)
#define NUM_MSGS (10)
/* Benchmark parameters */
Char localQueueName[6];
Char nextQueueName[6];
Char prevQueueName[6];
Char core_temp[6];
UInt numCores = 0;
UInt16 prevCoreId;
UInt16 selfId;
UInt64 timeAdj = 0;
Types_FreqHz timerFreq, cpuFreq;
/* Results */
UInt32 rawtimestamps[NUMLOOPS];
UInt32 latencies[NUMLOOPS - 1];
MessageQ_Handle messageQ =NULL;
MessageQ_QueueId prevQueueId;
MessageQ_QueueId nextQueueId,nextQueueId1,nextQueueId2,nextQueueId3,nextQueueId4,nextQueueId4,nextQueueId5,nextQueueId6,nextQueueId7;
UInt64 timeLength = 0;
Float cpuTimerFreqRatio;
Statistics latencyStats;
/* Descriptor pool [Size of descriptor * Number of descriptors] */
/* place this monolithic descritor pool in shared memory */
#pragma DATA_SECTION (monolithicDesc, ".desc");
#pragma DATA_ALIGN (monolithicDesc, 16)
UInt8 monolithicDesc[SIZE_MONOLITHIC_DESC * NUM_MONOLITHIC_DESC];
#define NUM_MSGS_TO_PREALLOC (8000)
#pragma DATA_SECTION (txMsgPtrs, ".msgQ_ptrs");
TstMsg *txMsgPtrs[NUM_MSGS_TO_PREALLOC];
#pragma DATA_SECTION (rxMsgPtrs, ".msgQ_ptrs");
TstMsg *rxMsgPtrs[NUM_MSGS_TO_PREALLOC];
/**
* @b Description
* @n
* This functions prints the statistics gathered for the transport during
* the latency test.
*/
void convertyuv422torgb565( unsigned char inbuf[],unsigned char outbuf[],int width,int height)
{
int rows,cols;
int y,u,v,r,g,b,rdif,invgdif,bdif;
int YPOS,UPOS,VPOS;
YPOS=0;
UPOS=1;
VPOS=3;
for(rows=0;rows<height;rows++)
{
for(cols=0;cols<width;cols++)
{
y = inbuf[YPOS+cols*2+rows*1920*2];
if(cols%2==0)
{
u = inbuf[UPOS+cols*2+rows*1920*2] - 128;
v = inbuf[VPOS+cols*2+rows*1920*2] - 128;
}else{
u = inbuf[UPOS+(cols-1)*2+rows*1920*2] - 128;
v = inbuf[VPOS+(cols-1)*2+rows*1920*2] - 128;
}
rdif = v + ((v * 103) >> 8);
invgdif = ((u * 88) >> 8) +((v * 183) >> 8);
bdif = u +( (u*198) >> 8);
r = y + rdif;
g = y - invgdif;
b = y + bdif;
r=r>255?255:(r<0?0:r);
g=g>255?255:(g<0?0:g);
b=b>255?255:(b<0?0:b);
*(outbuf++) =( ((g & 0x1C) << 3) | ( b >> 3) );
*(outbuf++) =( (r & 0xF8) | ( g >> 5) );
}
}
}
/**
* @b Description
* @n
* This function initalizes the platform. It has called at startup. This is defined in the
* .cfg file via the Startup.firstFxns.$add('&initPlatform'); definition.
*/
void initPlatform(void)
{
platform_init_flags pFormFlags;
platform_init_config pFormConfig;
/* Status of the call to initialize the platform */
UInt32 pFormStatus;
/* Only run on single core */
if (CSL_chipReadReg (CSL_CHIP_DNUM) == 0)
{
/*
* You can choose what to initialize on the platform by setting the following
* flags. Things like the DDR, PLL, etc should have been set by the boot loader.
*/
memset( (void *) &pFormFlags, 0, sizeof(platform_init_flags));
memset( (void *) &pFormConfig, 0, sizeof(platform_init_config));
pFormFlags.pll = 0; /* PLLs for clocking */
pFormFlags.ddr = 0; /* External memory */
pFormFlags.tcsl = 1; /* Time stamp counter */
pFormFlags.phy = 0; /* Ethernet */
pFormFlags.ecc = 0; /* Memory ECC */
pFormConfig.pllm = 0; /* Use libraries default clock divisor */
pFormStatus = platform_init(&pFormFlags, &pFormConfig);
/* If we initialized the platform okay */
if (pFormStatus != Platform_EOK)
{
/* Initialization of the platform failed. */
System_printf("Platform failed to initialize. Error code %d \n", pFormStatus);
}
}
}
void convert_func(){
Int status;
int i;
//UInt numReceived;
MessageQ_Msg msg[7];
//UInt64 timeStamp=0;
//UInt64 timeAdj=0;
//double throughPut;
if (selfId == 0) {
System_printf("tsk0. selfproc=%d nextQueueName (%s) openned, nextQueueId=%d-%d-%d-%d-%d-%d-%d\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE1-7", nextQueueId1,nextQueueId2,nextQueueId3,nextQueueId3,nextQueueId4,nextQueueId5,nextQueueId6,nextQueueId7);
for(i=0;i<=6;i++){
msg[i]= MessageQ_alloc(HEAP_ID, MESSAGE_SIZE_IN_BYTES);
if (msg[i]== NULL) {
System_abort("MessageQ_alloc failed\n");
}
}
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE1", msg[0]);
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE2", msg[1]);
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE3", msg[2]);
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE4", msg[3]);
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE5", msg[4]);
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE6", msg[5]);
System_printf("tsk0. selfProc=%d calling MessageQ_put(nextQueueName=%s). msg=0x%x\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE7", msg[6]);
while(*((volatile unsigned int *)LEGACY_A_IRQ_STATUS_RAW)!=1)
{}
System_printf("get interrupt from 8168\n");
status = MessageQ_put(nextQueueId1, msg[0]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId2, msg[1]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId3, msg[2]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId4, msg[3]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId5, msg[4]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
status = MessageQ_put(nextQueueId6, msg[5]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
} status = MessageQ_put(nextQueueId7, msg[6]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
System_printf("core 0 MessageQ_put done\n");
//System_printf("convert start\n");
/* Take time at start of test */
//timeStamp = getStartTime64();
convertyuv422torgb565( (uint8_t *)0x90000000,(uint8_t *)0x91000000,1920,1080/8);
//PCIE Interrupt
/* clear PCIE interrupt */
DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1);
DEVICE_REG32_W(PCIE_IRQ_EOI, 0x0);
for(i=0;i<=6;i++){
status = MessageQ_get(messageQ, &msg[i], MessageQ_FOREVER);
if (status < 0) {
System_abort("MessageQ_get failed\n");
}
System_printf("MessageQ_get %d time\n",i);
}
System_printf("convert done\n");
/* Get execution time to transfer all messages */
//timeLength = getExecutionTime64(timeStamp, timeAdj);
//throughPut = (double)CYCLES_TO_US(timeLength, 1000000000);
//System_printf("covert time is %f us\n",throughPut);
//��DDR 91000000����ʼ����ת����rgb����
// FILE *fp2;
// fp2=fopen("conpspyzj.rgb","ab");
// fwrite((void *)0x91000000, 1, 720*480*2, fp2);
// fclose(fp2);
for(i=0;i<=6;i++)
MessageQ_free(msg[i]);
System_printf("MessageQ_free\n");
/* generate interrupt to host */
*((volatile uint32_t *)PCIE_EP_IRQ_SET) = 0x1;
System_printf("INTERRUPT TO A8\n");
}
else{
//System_printf("tsk0. selfproc=%d nextQueueName (%s) openned, nextQueueId=%d\n", CSL_chipReadReg (CSL_CHIP_DNUM), "CORE0", nextQueueId);
while(*((volatile unsigned int *)LEGACY_A_IRQ_STATUS_RAW)!=1)
{}
status = MessageQ_get(messageQ, &msg[selfId-1], MessageQ_FOREVER);
if (status < 0) {
System_abort("MessageQ_get failed\n");
}
System_printf("core %d MessageQ_get done\n",selfId);
convertyuv422torgb565( (uint8_t *)(0x90000000+(1920*1080/4)*selfId),(uint8_t *)(0x91000000+(1920*1080/4)*selfId),1920,1080/8);
//System_printf("core %d call MessageQ_put\n ",selfId);
status = MessageQ_put(nextQueueId, msg[selfId-1]);
if (status < 0) {
System_abort("MessageQ_put failed\n");
}
System_printf("core %d MessageQ_put done\n",selfId);
}
}
/**
* @b Description
* @n
* This configures the descriptor region and initializes CPPI, and QMSS.
* This function should only be called once per chip.
*
* @retval
* Success - 0
* @retval
* Error - <0
*/
Int32 systemInit (Void)
{
Qmss_InitCfg qmssInitConfig; /* QMSS configuration */
Qmss_MemRegInfo memInfo; /* Memory region configuration information */
Qmss_Result result;
UInt32 coreNum;
coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
System_printf ("\n-----------------------Initializing---------------------------\n");
System_printf ("Core %d : L1D cache size %d. L2 cache size %d.\n", coreNum, CACHE_getL1DSize(), CACHE_getL2Size());
memset ((Void *) &qmssInitConfig, 0, sizeof (Qmss_InitCfg));
/* Set up the linking RAM. Use the internal Linking RAM.
* LLD will configure the internal linking RAM address and maximum internal linking RAM size if
* a value of zero is specified.
* Linking RAM1 is not used */
qmssInitConfig.linkingRAM0Base = 0;
qmssInitConfig.linkingRAM0Size = 0;
qmssInitConfig.linkingRAM1Base = 0;
qmssInitConfig.maxDescNum = NUM_MONOLITHIC_DESC /*+ total of other descriptors here */;
#ifdef xdc_target__bigEndian
qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);
#else
qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);
#endif
/* Initialize Queue Manager SubSystem */ //Qmss_init
result = Qmss_init (&qmssInitConfig, &qmssGblCfgParams);
if (result != QMSS_SOK)
{
System_printf ("Error Core %d : Initializing Queue Manager SubSystem error code : %d\n", coreNum, result);
return -1;
}
//Cppi_init
result = Cppi_init (&cppiGblCfgParams);
if (result != CPPI_SOK)
{
System_printf ("Error Core %d : Initializing CPPI LLD error code : %d\n", coreNum, result);
}
System_printf ("address of monolithicDesc[] = 0x%x. Converted=0x%x\n", monolithicDesc, l2_global_address ((UInt32) monolithicDesc));
/* Setup memory region for monolithic descriptors */
memset ((Void *) &monolithicDesc, 0, SIZE_MONOLITHIC_DESC * NUM_MONOLITHIC_DESC);
memInfo.descBase = (UInt32 *) monolithicDesc; /* descriptor pool is in MSMC */
memInfo.descSize = SIZE_MONOLITHIC_DESC;
memInfo.descNum = NUM_MONOLITHIC_DESC;
memInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
memInfo.memRegion = (Qmss_MemRegion) descriptorMemRegion;
memInfo.startIndex = 0;
result = Qmss_insertMemoryRegion (&memInfo);
if (result < QMSS_SOK)
{
System_printf ("Error Core %d : Inserting memory region %d error code : %d\n", coreNum, memInfo.memRegion, result);
return -1;
}
else
{
System_printf ("Core %d : Memory region %d inserted\n", coreNum, result);
}
/* Writeback the descriptor pool. Writeback all data cache.
* Wait until operation is complete. */
Cache_wb (monolithicDesc,
SIZE_MONOLITHIC_DESC * NUM_MONOLITHIC_DESC,
Cache_Type_ALLD, TRUE);
return 0;
}
/**
* @b Description
* @n
* Task which kicks off the latency and throughput tests
*/
Void tsk0(UArg arg0, UArg arg1)
{
Int status;
System_printf("tsk0 starting\n");
/* Register this heap with MessageQ */
if(selfId==0){
MessageQ_registerHeap((IHeap_Handle)SharedRegion_getHeap(0), HEAP_ID);
/* Open the 'next' remote message queue. Spin until it is ready. */
do {
status = MessageQ_open("CORE1", &nextQueueId1);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE2", &nextQueueId2);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE3", &nextQueueId3);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE4", &nextQueueId4);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE5", &nextQueueId5);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE6", &nextQueueId6);
Task_yield();
}
while (status < 0);
do {
status = MessageQ_open("CORE7", &nextQueueId7);
Task_yield();
}
while (status < 0);
}
else{
MessageQ_registerHeap((IHeap_Handle)SharedRegion_getHeap(0), HEAP_ID);
System_sprintf(core_temp, "CORE%d", selfId);
do {
status = MessageQ_open(core_temp, &nextQueueId);
Task_yield();
}
while (status < 0);
}
while(1)
{
convert_func();
}
detachAll(MultiProc_getNumProcessors());
System_exit(0);
}
/**
* @b Description
* @n
* Main - Initialize the system and start BIOS
*/
Int main(Int argc, Char* argv[])
{
Int32 result = 0;
Types_Timestamp64 time64;
UInt64 timeStamp = 0;
Timestamp_getFreq(&timerFreq); //Get the timestamp timer's frequency (in Hz) ��ʱ��
System_printf("timerFreq.lo = %d. timerFreq.hi = %d\n", timerFreq.lo, timerFreq.hi);
BIOS_getCpuFreq(&cpuFreq); //Get CPU frequency in Hz
System_printf("cpuFreq.lo = %d. cpuFreq.hi = %d\n", cpuFreq.lo, cpuFreq.hi);
cpuTimerFreqRatio = (Float)cpuFreq.lo / (Float)timerFreq.lo; //=1
Timestamp_get64(&time64); //Return a 64-bit timestamp
timeStamp = TIMESTAMP64_TO_UINT64(time64.hi,time64.lo);
timeAdj = TIMESTAMP64_TO_UINT64(time64.hi,time64.lo) - timeStamp; //=0
selfId = CSL_chipReadReg (CSL_CHIP_DNUM);
System_printf("Core (\"%s\") starting\n", MultiProc_getName(selfId));
if (numCores == 0) {
numCores = 8; //MultiProc_getNumProcessors(); Number of processors configured with MultiProc =2
}
if (selfId == 0)
{
/* QMSS, and CPPI system wide initializations are run on
* this core */
result = systemInit(); //systemInit
if (result != 0)
{
System_printf("Error (%d) while initializing QMSS\n", result);
}
iblPCIeWorkaround();//��ʼ��PCIE���ȴ�������ɡ�
DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1);
// FILE *fp1;
// fp1=fopen("conpsp.yuv","r");
// fread((void *)0x90000000,1,720*480*2,fp1);
// fclose(fp1);
// System_printf("fread done\n");
/* Attach all cores. */
attachAll(numCores);
System_printf("core 0 exec attachAll done\n");
// prevCoreId = "1/2/3/4/5/6/7";
//
System_sprintf(localQueueName, "CORE%d", selfId); //localQueueName��ȫ�ֱ���
// System_sprintf(nextQueueName, "CORE%s","1/2/3/4/5/6/7");
// System_sprintf(prevQueueName, "CORE%s", prevCoreId); //System_sprintf���Ǵ�ӡ����ʹprevQueueNameΪ��CORE%d���ַ���
//
// System_printf("localQueueName=%s. nextQueueName=%s. prevQueueName=%s\n",
// localQueueName, nextQueueName, prevQueueName);
/* Create a message queue. */
messageQ = MessageQ_create(localQueueName, NULL);
if (messageQ== NULL) {
System_abort("MessageQ_create failed\n" );
}
}
else{
iblPCIeWorkaround();//��ʼ��PCIE���ȴ�������ɡ�
/* Attach all cores. */
attachAll(numCores);
prevCoreId = 0;
System_sprintf(localQueueName, "CORE%d", selfId); //localQueueName��ȫ�ֱ���
System_sprintf(nextQueueName, "CORE%d",0);
System_sprintf(prevQueueName, "CORE%d", prevCoreId); //System_sprintf���Ǵ�ӡ����ʹprevQueueNameΪ��CORE%d���ַ���
System_printf("localQueueName=%s. nextQueueName=%s. prevQueueName=%s\n",
localQueueName, nextQueueName, prevQueueName);
/* Create a message queue. */
messageQ = MessageQ_create(localQueueName, NULL);
if (messageQ== NULL) {
System_abort("MessageQ_create failed\n" );
}
}
BIOS_start();
System_printf("done BIOS_start\n");
return (0);
}
the log is:
core0 it just in the messageQ_get, idle
3.third question:
if i do not use bios,can i use the messageQ module to IPC communication?i think can not,is it?
if i do not use bios,how can i do IPC communication,is there some example projects?
thanks. best regards
