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questions on Keystone 2 - ARM boot - PA - Multicore Navigator

rajanikanth g
Intellectual 520 points

Hi all,

I am using XTCIEVMK2X EVM. 

Developing environment is: CCS ver  5.4.0.00091; MCSDK Packages: 3_00_01_12

Bootmode:  ARM SPI Little Endian mode. 

ARM is using NFS file system.

Q1:

At present we have enabled Switch port 0 (Host Port) and Switch Port 1 (SGMII 0 Port).

For ARM SPI boot mode,  is it mandatory to enable Switch Port 2 (SGMII 1 Port) ? 

As ARM’s NFS file system continuously using Switch Port 1 (SGMII 0 Port), so how to manage of sending pkts to the application running on DSP ? For this, it is necessary to use Switch Port 2 (SGMII 1 Port) ? or single Switch Port 1 (SGMII 0 Port) can manage the pkt flow of both ARM and DSP’s application ?

Q2:

 Receiving pkts coming out of Switch port 0 (Host Port) via GbE switch are transferred to the PA’s classify engines L2, L3 and L4 respectively. After this screening, pkts will reach to Rx DMA and then to Rx queues.

It's responsibility of DSP application to manage the above flow (with the help if driver’s code) and my question is how ARM is managing these flow ?

In ARM SPI boot mode, Will ARM also internally follow the same approach by providing entries of MAC, IP and UDP info into lookup tables at PA level ?

Q3:

In ARM SPI boot mode, will ARM and DSP’s application maintain different Rx queues ? Are there any dedicated queues for ARM in ARM SPI boot mode?

If there are no separate queues for ARM and DSP’s application then how we need to manage the reading of data from Rx queues without any conflicts between ARM and DSP’s application ?

Please provide your inputs.

Thanks in advance.

Thanks and Regards,
Rajanikanth.

  • 0
    TI__Mastermind 20790 points

    Rajanikanth,

    A1:
    It is not necessary, you can use which is enabled port.
    Yes, you can manage the pkt flow of both ARM and DSP’s application through single port.

    A2:
    Please go through this wiki article, find more detailed information for network with PA.
    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Network_Driver
    You can find the steps for adding, deleting entries.

    A3:
    I think so, there is no dedicated queques for ARM or DSP. The resource manager module will take care about this. You see the test code at:
    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Developing_System_Mgmt#QMSS_LLD
    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Developing_System_Mgmt#DSP_.2B_ARM_Linux_Test_Project

  • 0 in reply to Pubesh
    Intellectual 520 points

    Hi Pubesh,

    Thanks for the answers.

    In the link:

    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Network_Driver

    I can see the below info:

    2) Stop:

    A standard netdev stop operation that stops the netif queue.
    It sets the receive state to teardown and calls dmaengine_pause APIs from the dmaengine layer to pause both the RX and TX channel.
    After NAPI is disabled, the operation goes onto release the dma channels by calling the dma_release_channel API.
    The RX state is set to invalid and the ethernet susbsystem is stopped

    Are there any commands available so that I can disable/pause kernal for being use of  CPSW / GbE Switch subsystem ?

    Thanks in advance.

    Thanks & Best regards,

    Rajanikanth.