DM3730 L3 at 200 MHz

MattB

Expert 2025 points

Other Parts Discussed in Thread: DM3730, OMAP3530

Hi,

I'm trying to migrate an existing project from the OMAP3530 to the AM/DM3730. This project runs on a custom board. We're using a Micron POP LPDDR that supports 200 MHz (it's a -5).

We want to run at the memory bus and the L3 Interconnect at 200 MHz because we think it might boost our throughput.

We're using the x-loader, U-Boot and kernel from the OMAP3530 DVSDK i.e. Linux V2.6.32.

Can anyone suggest what I need to do to the bootloaders and kernel so that I finish up running the L3 at 200 MHz?

I've tried some things for myself but I get this message from Linux:

Clocking rate (Crystal/Core/MPU): 26.0/200/600 MHz
Reprogramming SDRC clock to 200000000 Hz
dpll3_m2_clk rate change failed: -22

I don't think this is correct because at 166 MHz I get:

Clocking rate (Crystal/Core/MPU): 26.0/332/500 MHz
Reprogramming SDRC clock to 332000000 Hz

In other words, I think the core frequency should appear as twice the L3 frequency.

Any thoughts greatly appreciated!

Thanks,

Matt

over 11 years ago

0 Cvetolin Shulev-XID over 11 years ago

TI__Guru 65405 points

Hi Matt,

During investigating the dpll3_m2_clk rate change failed: -22 error message I suggest you both software and hardware OMAP35x To AM/DM37x migration guides which could be useful for migration of your project.

http://processors.wiki.ti.com/index.php/OMAP35x_To_AM37x_Hardware_Migration_Guide

http://processors.wiki.ti.com/index.php/OMAP35x_To_AM37x_Software_Migration_Guide

Tsvetolin Shulev

0 MattB over 11 years ago in reply to Cvetolin Shulev-XID

Expert 2025 points

Hi Tsvetolin,

I'm using a kernel which did not come from the DM3730 DVSDK. The kernel I'm using, 2.6.32, originate on the OMAP3530 DVSDK. I want to see if I can get our existing software working before deciding whether we need to update X-Loader, U-Boot and Linux.

I'm trying to understand whether the kernel (V2.6.32) decides how to configure the DPLLs for itself or whether the register state left by U-Boot is important.

Any ideas?

Thanks,

Matt

0 MattB over 11 years ago

Expert 2025 points

As far as I can tell Linux reads the DPLL registers and uses the existing values as the basis for its configuration. The DPLL registers are not changed by U-Boot so it is X-Loader that is determining the Core DPLL configuration.

In prcm_init in X-Loader I found the following:

	/* If the input clock is greater than 19.2M always divide/2 */
	/*
	 * On OMAP3630, DDR data corruption has been observed on OFF mode
	 * exit if the sys clock was lower than 26M. As a work around,
	 * OMAP3630 is operated at 26M sys clock and this internal division
	 * is not performed.
	 */
	if((is_cpu_family() != CPU_OMAP36XX) && (sys_clkin_sel > 2)) {
		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
		clk_index = sys_clkin_sel/2;
	} else {
		sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
		clk_index = sys_clkin_sel;
	}

I think this explains why I see:

Clocking rate (Crystal/Core/MPU): 26.0/200/600 MHz

(core = 200 MHz) rather than:

Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz

(core = 400 MHz)

Unfortunately I don't really understand what it means!

Is X-Loader doing the correct thing?

Does Linux understand that Core DPLL3 has been configured without the divide by 2?

Matt

0 MattB over 11 years ago in reply to MattB

Expert 2025 points

The problem is related to our mix of the different loaders and Linux.

As described above X-Loader V1.51 (practically the latest) runs sys_clk at 26 MHz. Whereas before it has always been normal to divide the 26 MHz osc_sys_clk and have sys_clk at 13 MHz.

We're using U-Boot from the OMAP3530 DVSDK and it gets confused because the divider isn't 2. I had thought that U-Boot wasn't changing the configuration but it has its own function called prcm_init which is configuring sys_clk.

The DM3730 DVSDK has a later U-Boot and its prcm_init does the same thing with osc_sys_clk.

I made prcm_init in my U-Boot set sys_clkto 26 MHz and I got:

Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz
Reprogramming SDRC clock to 400000000 Hz

I think it is working as I expect now but I'm still not sure whether I should attempt to update U-Boot and/or Linux to the DM3730 DVSDK versions. I shall think about it tomorrow!

Matt

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DM3730 L3 at 200 MHz