How can I know whether the DM8168 has captured a frame?

Haoran Li1

Hi,

I am now using EVM8168 + Custom FPGA board. I managed to verify my dummy 1080p30 BT.1120 frame. The pins are connected like this:

FPGA Y_Out[7:0] ===> VIN Port[15:8]

FPGA CbCr_Out[7:0] ===> VIN Port[7:0]

74.25MHz Clk ===> VIN0_CLKA

I modified my 1080p60 Capture + Disp usecase to an 1080p30 one. And my FPGA would continuously generate 1080p30 BT.1120 video frame once powered. I tried to run the 1080p30 Capture + Display usecase. However, the monitor display nothing as if there were no video signal on the VIN0 Port. Although I have my verilog HDL verified by using Modelsim, I eager to know whether the DM8168 provides some usecase or some relevant register which concerned about the capture link.

Could you please give me some tips? How can I confirm the DM8168 has successfully detected my video frame?

Naroah

Mar/17/2014

over 11 years ago

0 Marvin Woo over 11 years ago

Intellectual 560 points

hi,Li

1.when the demo running ,press i,then you will see the input information (such as fps,resolution) of capture mould .

2.if you are using Altera Fpga,you could use SingalTapII to read the register of you Fpga,then you will see the data output.

Good luck

0 David Soto - RidgeRun over 11 years ago

Genius 3700 points

Hi,

Also, in case of using the EZSDK you can try using the capture_encode demo which would use OMX to capture from the VIP0 and display through HDMI. You just need to remove the TVP component since it is present just in the EVMs and since you are using a FPGA to feed video and not a TVP you need to remove it. You can use the patch attached to do it. Using this demo you should be able to verify if you are getting frames.

-David

Fullscreen 4530.remove-tvp-from-capture-encode-demo.patch.txt Download

Index: ezsdk-5_05_02_00/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient.c
===================================================================
--- ezsdk-5_05_02_00.orig/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient.c	2014-02-11 09:18:32.975211744 -0600
+++ ezsdk-5_05_02_00/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient.c	2014-03-17 07:39:12.859100783 -0600
@@ -723,6 +723,7 @@
 
   pAppData->capILComp->handle = pAppData->pCapHandle;
 
+#if USE_TVP
   /* This is control component, without ports. It is implemented as OMX
      component */
   eError =
@@ -738,6 +739,7 @@
             IL_ClientErrorToStr (eError));
     goto EXIT;
   }
+#endif
 
   /* Configute the capture componet */
   /* calling OMX_Setparam in this function */
@@ -908,13 +910,12 @@
                               OMX_VFPC_OUTPUT_PORT_START_INDEX,
                               pAppData->disILComp,
                               OMX_VFDC_INPUT_PORT_START_INDEX);
-
 /******************************************************************************/
 
   /* OMX_SendCommand expecting OMX_StateIdle, after this command component will 
      wait for all buffers to be allocated as per omx buffers are created during 
      loaded to Idle transition IF ports are enabled ) */
-
+#if USE_TVP
   eError =
     OMX_SendCommand (pAppData->pTvpHandle, OMX_CommandStateSet,
                      OMX_StateIdle, NULL);
@@ -926,7 +927,7 @@
   }
 
   semp_pend (pAppData->capILComp->done_sem);
-
+#endif
   eError =
     OMX_SendCommand (pAppData->pCapHandle, OMX_CommandStateSet,
                      OMX_StateIdle, NULL);
@@ -1221,7 +1222,7 @@
   semp_pend (pAppData->capILComp->done_sem);
 
   printf (" capture state execute \n ");
-
+#if USE_TVP
   eError =
     OMX_SendCommand (pAppData->pTvpHandle, OMX_CommandStateSet,
                      OMX_StateExecuting, NULL);
@@ -1232,10 +1233,11 @@
     goto EXIT;
   }
 
+
   semp_pend (pAppData->capILComp->done_sem);
 
   printf (" capture control ( TVP ) state execute \n ");
-
+#endif
 /******************************************************************************/
 
   /* Create thread for writing bitstream and passing the buffers to encoder
@@ -1347,6 +1349,7 @@
   semp_pend (pAppData->capILComp->done_sem);
   printf (" capture state idle \n ");
 
+#if USE_TVP
   /* change state to idle so that buffers processing would stop */
   eError =
     OMX_SendCommand(pAppData->pTvpHandle, OMX_CommandStateSet,
@@ -1360,7 +1363,7 @@
 
   semp_pend(pAppData->capILComp->done_sem);
   printf(" control tvp state idle \n ");
-
+#endif
 
   /* change state to idle so that buffers processing can stop */
   eError =
@@ -1584,6 +1587,7 @@
 
   printf (" capture state loaded \n ");
 
+#if USE_TVP
   /* ctrl tvp component does not alloc/free any data buffers, It's interface
      is though as it is omx componenet */
   eError =
@@ -1599,6 +1603,7 @@
   semp_pend(pAppData->capILComp->done_sem);
 
   printf(" ctrl-tvp state loaded \n ");
+#endif
 
 /******************************************************************************/
 
@@ -1613,6 +1618,7 @@
   }
   printf (" capture free handle \n");
 
+#if USE_TVP
   eError = OMX_FreeHandle(pAppData->pTvpHandle);
   if ((eError != OMX_ErrorNone))
   {
@@ -1622,6 +1628,7 @@
   }
 
   printf(" ctrl-tvp free handle \n");
+#endif
 
   eError = OMX_FreeHandle (pAppData->pEncHandle);
   if ((eError != OMX_ErrorNone))
Index: ezsdk-5_05_02_00/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient.h
===================================================================
--- ezsdk-5_05_02_00.orig/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient.h	2014-02-11 09:18:32.927211744 -0600
+++ ezsdk-5_05_02_00/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient.h	2014-03-17 07:38:24.967101120 -0600
@@ -53,7 +53,7 @@
 extern "C"
 {                               /* be compiled by a C++ compiler */
 #endif
-
+#define USE_TVP 0
 #define IL_CLIENT_MAX_NUM_IN_BUFS  16
 #define IL_CLIENT_MAX_NUM_OUT_BUFS 16
 
@@ -188,8 +188,13 @@
 /* ========================================================================== */
 typedef struct IL_Client
 {
+#if USE_TVP
   OMX_HANDLETYPE pCapHandle, pDeiHandle, pDisHandle, pctrlHandle, pTvpHandle,
                  pEncHandle;
+#else
+  OMX_HANDLETYPE pCapHandle, pDeiHandle, pDisHandle, pctrlHandle,
+                 pEncHandle;
+#endif
   OMX_COMPONENTTYPE *pComponent;
   OMX_CALLBACKTYPE pCb;
   OMX_STATETYPE eState;
Index: ezsdk-5_05_02_00/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient_utils.c
===================================================================
--- ezsdk-5_05_02_00.orig/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient_utils.c	2014-02-11 09:18:32.939211744 -0600
+++ ezsdk-5_05_02_00/ezsdk/component-sources/omx_05_02_00_48/examples/ti/omx/demos/capture_encode/src/ilclient_utils.c	2014-03-17 07:38:24.983101119 -0600
@@ -63,6 +63,7 @@
 #include <OMX_TI_Index.h>
 /*---------------------- function prototypes ---------------------------------*/
 /* None */
+#define USE_TVP 0
 
 void usage (IL_ARGS *argsp)
 {
@@ -1017,15 +1018,15 @@
                             (OMX_INDEXTYPE) OMX_TI_IndexConfigVFCCFrameSkip,
                             (OMX_PTR) & sCapSkipFrames);
   }
-
+#if USE_TVP
   /* Set parameters for TVP controller */
-
   OMX_INIT_PARAM (&sHwPortId);
   /* capture on EIO card is component input at VIP1 port */
   sHwPortId.eHwPortId = OMX_VIDEO_CaptureHWPortVIP1_PORTA;
   eError = OMX_SetParameter (pAppData->pTvpHandle,
                              (OMX_INDEXTYPE) OMX_TI_IndexParamVFCCHwPortID,
                              (OMX_PTR) & sHwPortId);
+
   OMX_INIT_PARAM (&sHwPortParam);
   sHwPortParam.eCaptMode = OMX_VIDEO_CaptureModeSC_NON_MUX;
   sHwPortParam.eVifMode = OMX_VIDEO_CaptureVifMode_16BIT;
@@ -1076,6 +1077,7 @@
                              (OMX_PTR) & sVidDecParam);
   if (eError != OMX_ErrorNone)
     ERROR ("failed to set Ctrl Vid dec info \n");
+#endif
 
   return (eError);
 }

0 Haoran Li1 over 11 years ago in reply to Marvin Woo

Expert 1850 points

Hi Marvin,

Thank you for your reply.

You do give me a insight! Actually, I am using an Altera Cyclone IV FPGA. I doubt there was something wrong with my Hardward Description. I will try to debug them out.

By the way, in FPGA, I try to clock out my video frame at the falling edge of the sync clock. It seems DM8168 would sample at the rising edge of the sync clock, isn't it?

Naroah

Mar/18/2014

0 Marvin Woo over 11 years ago in reply to Haoran Li1

Intellectual 560 points

Hi,Li

there is no sync clock used when use embedded sync format.

output data at falling edge of data clock is correct.

BT1120 data format as follow:

Y:FF0000XXDATAFF0000XX

CB/CR:FF0000XXDATAFF0000XX

need not CRC,and make sure data<255 ,in BT1120,data should <235,but 254 seems work well.

Good Luck

0 Haoran Li1 over 11 years ago in reply to Marvin Woo

Expert 1850 points

Hi Marvin,

Yes, I take advantage of the 16-bit embedded sync words (EAV / SAV), not the discrete sync signals (Field HSYNC VSYNC).

I tried to generate such a frame by my FPGA:

I didn't take care of the LineNumber Field and CRC Field in the timing of digital line blanking. Actrually, these data are filled by 0x10. But according to your words, it seems that I shall not using the digital blanking at all, shan't I?

In other word, I think a complete line data steam is like this:

EAV (0xFF 0x00 0x00 0xXY) ==> ANC (272 words) ==> SAV(0xFF 0x00 0x00 0xXY) ==> ACTIVEDATA(1920 words) ===> EAV(Next Line) ...

Marvin Woo said:

BT1120 data format as follow:

Y:FF0000XXDATAFF0000XX

CB/CR:FF0000XXDATAFF0000XX

Referring to this, shall I make my line sequence like this?

SAV(0xFF 0x00 0x00 0xXY) ==> ACTIVEDATA(1920 words) ===> EAV(0xFF 0x00 0x00 0xXY) ==> SAV(Next Line) ...

Shall I leave out all the Digital Blanking Field (Ancillary data)?

Naroah

Mar/18/2014

0 Marvin Woo over 11 years ago in reply to Haoran Li1

Intellectual 560 points

Hi,Li

Ancillary data i just use 1 line.L1-L41,L1122-L1125, i just use 1 line .it accord to your camera output feature.

You are right.but my design format (1 frame)as follow:

EAV-anc(need not be 272)-SAV DATA

EAV-anc(need not be 272)-SAV anc data

i use this format.but the vip capture detect data by EAV and SAV,so if you can generate EAV and SAV accord to your camera(hs,vs,or FVAL LVAL DE), your FPGA will output embedded sync data correctly.

0 Marvin Woo over 11 years ago in reply to Marvin Woo

Intellectual 560 points

Hi,Li

you can use the open source SMPTE292 VHD demo to generate BT1120 data

Good luck

0 Haoran Li1 over 11 years ago in reply to Marvin Woo

Expert 1850 points

Hi Marvin,

Thank you for your awfully informative tips! That's very kind of you.

Anyway, I will try to debug my Verilog HDL.

Wish a good luck!

Naroah

Mar/18/2014

0 Brijesh Jadav over 11 years ago in reply to Haoran Li1

TI__Guru**** 479785 points

Hi Naroah,

There are VIP registers which will report received frame size when it gets corret frame, you could look into it to know if vip is receiving frames or not.

Regards,

Brijesh

0 Haoran Li1 over 11 years ago in reply to Marvin Woo

Expert 1850 points

Hi Marvin,
   You do give me such a great help!
   I have successfully capture the FPGA-generated ColorBar frame!
   Thank you for your help; and I have set your answer verified.

Naroah
Mar/18/2014

0 Marvin Woo over 11 years ago in reply to Haoran Li1

Intellectual 560 points

Hi,Li

congratulation!

can you help me ?

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/328294.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/326270.aspx

thank you

0 David Soto - RidgeRun over 11 years ago in reply to Brijesh Jadav

Genius 3700 points

Hi Brijesh,

Which are the registers for each VIP?

Thanks,

-David

0 Brijesh Jadav over 11 years ago in reply to David Soto - RidgeRun

TI__Guru**** 479785 points

Hi David,

You could get the frame size from the offset 0x48105530 for channel 0 of VIP0A. So if VIP is reporting some correct frame size here in this register, vip is able to receive the frames correctly. otherwise there is some problem.

Regards,

Brijesh

0 David Soto - RidgeRun over 11 years ago in reply to Brijesh Jadav

Genius 3700 points

Great! Thanks for the info Brijesh!

0 Franck M over 10 years ago

Prodigy 10 points

Hi Li, Hi Marvin,

I am sorry to reply to an old post but I'm trying to make exactly the same thing as you and I don't undestand correctly what you are saying in the thread.

First of all, Marvin, you hare saying "output data at falling edge of data clock is correct." whereas I have found in this thread :

e2e.ti.com/.../228820

that "DM8168 is sampling data as falling edge of pixel clock".

In the BT 1120, it is saying that sampling is on the rising edge, so the data should be outputed at falling edge of data clock.

I have tried both but nothing is working :)

Marvin, you also say that ancillary data need not be 272. But can you confirm that blancking pixel need to be 272 between EAV and SAV ? Do you change EAV and SAV if the line is real image data or not ? I have undestood in the BT1120 that EAV and SAV should be :
- B6 / AB on lines L1-L41 and L1121-L1125
- 9D / 80 on others

I personnaly don't need to put ancillary data, so I just fill pixel with blanking pattern but it does not working.

Thank you.

Franck

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How can I know whether the DM8168 has captured a frame?