DM816x - SPRS614E - register update

Hi,

It's more likely typo fix from the previous version. Table 8-15 has indicated SYSCLK8 supporting 3 speed range blank (380 MHz), 2 (380 MHz) and 4 (450 MHz). However the previous version Table 8-16 showed 400 MHz. If there is no speed range indicated in the speed range column, it means blank speed. Therefore the change made at Table 8-16 SYSCLK8 is matching to Table 8-15 SYSCLK8 blank speed.

If customer want to use 400MHz SYSCLK8, customer should use speed range 4 devices.

Regards,

Hyun

That does help with one of the question I had.

What is the dependency on sysclk8 in regards to the DDR clock?

Does the sysclk8 = (DDR clock)/2 ?   e.g. DDR = 796.5, therefore sysclk8 should be 398.250?

If so, this seems to indicate you can run a DDR3 at a 800 Mhz, unless you have a speed range 4 device.

Phillip Dingman said:

What is the dependency on sysclk8 in regards to the DDR clock?

Does the sysclk8 = (DDR clock)/2 ?   e.g. DDR = 796.5, therefore sysclk8 should be 398.250?

If so, this seems to indicate you can run a DDR3 at a 800 Mhz, unless you have a speed range 4 device.

The DDR interface has multiple different clocks.  SYSCLK8 relates to the internal bus interface, i.e. it's used for the connection to the L3 interconnect (OCP).  There's a separate clock for the actual interface, i.e. what you would see on the actual pins.  I've marked up the clock diagram to help clarify:

Brad

Thanks for the reply, but that does not answer my question.  How should sysclk8 be set?

In the DDR PLL diagram (as you noted above), note sysclk8(OCP clock) is driving the DDR2/3 controller and DMM blocks. 

The DDR clock that you note is divided by /2 down stream to feed the DDR2/3 block as well. The diagram indicates 400 Mhz clock but its really DDR clock/2. 

My question:  Does sysclk8 need to be the same as DDR clock/2?  If this is true, then in order to have a DDR clock of 800 Mhz, the sysclk8 must be set to 800 Mhz/2 = 400 Mhz.  In which case, the only Ti8168 part that can achieve that is the one with a speed rating of 4.  

If this is not true, please clarify any system dependency (ignoring power consumption consideration) to determine the correct setting of sysclk8 (sysclk8 >= ClockX/Y ??).  Perhaps there are no dependencies and I can set it to the max allowed for sysclk8 given the device speed rating.  However, the TI documentation seems to indicate otherwise.

Hi,

  I think these threads are similar:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/336474/1177258.aspx#1177258

-David