FPGA and DSP connnected with SRIO(4x, 1port, 3.125Gbps),FPGA push data to DSP MSM with doorbell notify, DSP call Srio_sockSend_DIO API to do maintenance READ/WRITE and check some status, the logical layer error occur frequently when i run my test program. but this error could NOT be found if i trace my test program step by step in debugger.
some register value list as follow when error occur at first time:
[
LSU0_ICSR,=>0x00010000, bit ICS16 set,transaction complete with error
ERR_RST_EVNT_ICSR,=>0x00000004,bit ICS2 set, logical layer error management event capture
ERR_DET,=>0
SRIO_H_ADDR_CAPT=0x00000000
SRIO_ADDR_CAPT=0x0002002c
SRIO_ID_CAPT=0xffffbeef
SRIO_CTRL_CAPT=0x80000000
]
