This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Synchronous FIFO EMIF read length

I have a C6416 that I'm trying use to transfer data from a Xilinx standard FIFO.  I want to use the synchronous FIFO read over EMIF as described in the EMIF reference guide 2008.  Is Figure 4-21 supposed to be an example of 6 consecutive EMIF FIFO reads, or an specification that the bursts over the EMIF should be of length 6?

 

I was under the impression that SRE will be the length of N instructions if N reads are done consecutively (say via DMA), thus CE will be the same length as SRE in CEEXT = 0 (no glue) mode.  The diagram is showing an example of N=6.  My colleague interpreted this diagram as a specification that CE is enabled for 6 instructions.

 

Also, I've seen posts regarding the need for setting the INC in the DMA config to get the addressing to change as part of the protocol.  Is that confirmed to be necessary for a C6416?  I couldn't find one marked solved.

  • Hi Aaron,

    Moved this thread to correct forum.

    Thanks.

  • Aaron,

    Figure 4-21 in the EMIF Reference Guide (SPRU266E) shows an example of reading six samples from the EMIF. There is no requirement for always doing 6-word reads or writes.

    It would be helpful to provide a link to a post that you reference. I have no idea what that post was saying.

    You can see from Figure 4-21 that the EA signals are changing on each clock cycle. This means the address is incrementing, so that implies to me that the DMA should be generating incrementing addresses to support a burst. But without trying it and looking at the EA pins during an operation, I cannot provide a confirmed answer, only an observation from how the Figure is drawn. If you see different results when you try this on your hardware, please let us know.

    Regards,
    RandyP

  • I've just confirmed that you do not need to have the DMA increment the source address to trick the EMIF into handling the control signals properly.  I tried to find the message board post that I was referencing but didn't find it after a cursory search.

     

    Thanks,

    Aaron