I have a C6416 that I'm trying use to transfer data from a Xilinx standard FIFO. I want to use the synchronous FIFO read over EMIF as described in the EMIF reference guide 2008. Is Figure 4-21 supposed to be an example of 6 consecutive EMIF FIFO reads, or an specification that the bursts over the EMIF should be of length 6?
I was under the impression that SRE will be the length of N instructions if N reads are done consecutively (say via DMA), thus CE will be the same length as SRE in CEEXT = 0 (no glue) mode. The diagram is showing an example of N=6. My colleague interpreted this diagram as a specification that CE is enabled for 6 instructions.
Also, I've seen posts regarding the need for setting the INC in the DMA config to get the addressing to change as part of the protocol. Is that confirmed to be necessary for a C6416? I couldn't find one marked solved.