TMS320DM8168 Video out interface query

Hello,

i could answer your first question,

VENC only supports rising edge and it is not configurable.

Rgds,

Brijesh

Hello Brijesh,

I would appreciate if you would provide the reference in datasheet or reference manual which supports your statement.

Also, would be great if someone could provide feedback on other queries.

Thanks & Regards,

Roma

It should be there in HDVPSS TRM.

Rgds,

Brijesh

The fact that the datasheet/TRM do not provide a control register for the clock polarity supports the statement that this polarity cannot be controlled :-)

If a control existed it would be documented.

For Q2) the output load capacitance is 15pF as you have noted. The target impedance is assumed to be high, hence the capacitance is dominant.

For Q3) the datasheet states the max and min absolute times across all process, temperature and voltage corners, and are absolute values. It is meaningless to know how this varies since your system must be designed to accommodate the corners. If not then there is no guarantee you will meet timing in all your systems with all devices that are provided by TI.

BR,

Steve

Hello Steve,

Thank you for your response.

To give a brief on the problem we are facing, is that we are using VOUT[0] bus (24-bit at 148.5MHz) to interface to  HDMI transmitter IC whose setup timing requirement is 0nsec and hold timing requirement is 2nsec.

Using TMS320DM8168's tpd (min) formula of 0.27* tcyc, we get minimum propagation delay from TMS320DM8168 as 1.8nsec.
To calculate worst case hold timing margin, hold margin= [min. propagation delay + trace skew (based on rise time/ hold time)]- hold requirement of receiver.
Thus, we are getting hold timing failure by a margin of 200ps in our case (theoretical)

Our understanding of tpd minimum is that it is computed for best case process variation, fast temperature corner and highest permissible voltage i.e., 3.6V
Datasheet states operating condition as -40 Deg. C to 105 Deg. C.; whereas IBIS model states operating condition as -40 Deg. C to 125 Deg. C.

For our target application, we will not be operating the IC at -40 Deg. C. (will be above 0 Deg. C.) so in that case, we would like to know if we have some leeway for tpd min computation and if we can consider some formula for our application specific requirement. If so, pls help us with it.

We would also like to know percentage dependency of tpd (minimum) on voltage, temperature and process variation.
tpd min = x% of temperature variation + y% of voltage variation + z% of process variation

Suppose if we guarantee on our board voltage variation of less than 2%, and fast corner is at 0 Deg. C., then pls let us know what formula can we now use for tpd (min).

We would appreciate if you would help us in understanding and resolving above stated issues at the earliest, as we otherwise have to look at some other HDMI transmitter IC and this will cause major project delays.

Thanks & Regards,
Roma Bhagat

Unfortunately there is not a simple formula for this and the results may not even be monotonic over a given parameter shift, especially process which is itself an extremely complex mix.

My recommended solution is to a) ensure that the data trace lengths are matched extremely closely, are very well impedance matched, reference the same ground plane, are routed on the same layer for the same lengths (remember propagation delay changes with distance to the reference plane), have the same number of vias etc... then adjust the clock length to adjust the clock to data skew.

A very rough rule of thumb is 150ps/inch for microstrip, so try to skew your clock and data by an inch or so (data longer than clock) to increase your hold time.

BR,

Steve