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Hi Max,
The DM3725/30 processors (which are derivative of the omap35xx processor) are capable to encode H.264 BP up to 720p but with codecs using hardware encoder. You can obtain more detailed information about encoder benchmarking and parameters from the OMAP3 H.264 Encoder Quality Analysis and Benchmarking article at the link below:
http://www.ti.com/lit/an/sprabg4/sprabg4.pdf
Also you can pay attention whether your processors operates at the maximum frequency.
BR
Tsvetolin Shulev
Hi Tsvetolin
Thanks!
Currently, the processor is working on 800MHz. According to the DM37x DVSDK release notes, the H264 encoder performance is improved from 4.02, however, we used the example application of this version to test it with benchmark option, the encoder is still takes about 35-36ms, see the log of the application. Do you have any suggestion to improve this since this can't match 30fps encoding performance?
Frame 0: Read UYVY frame size 614400 (640x480) from file
Read time: 24139us
[1] Encode: 72542us
File write time: 763us
Total: 97444us
Frame 1: Read UYVY frame size 614400 (640x480) from file
Read time: 23406us
[2] Encode: 35917us
File write time: 336us
Total: 59689us
Frame 2: Read UYVY frame size 614400 (640x480) from file
Read time: 23378us
[3] Encode: 35401us
File write time: 580us
Total: 59389us
Frame 3: Read UYVY frame size 614400 (640x480) from file
Read time: 23376us
[4] Encode: 35675us
File write time: 518us
Total: 59600us
Frame 4: Read UYVY frame size 614400 (640x480) from file
Read time: 23377us
[5] Encode: 35583us
File write time: 458us
Total: 59449us
Frame 5: Read UYVY frame size 614400 (640x480) from file
Read time: 23376us
[6] Encode: 35461us
File write time: 580us
Total: 59447us
Frame 6: Read UYVY frame size 614400 (640x480) from file
Read time: 23377us
[7] Encode: 35553us
File write time: 457us
Total: 59387us
Hi Max,
According your measurement the time for encoding about 35 - 36 ms represents to 27.5 - 28.5 fps which is very closer to the target of 30 fps. Also I saw that your dm3725 operates at 800 MHz but it is capable to operates at 1 GHz. Therefore I suggest you try to change the frequency to 1 GHz. The easiest way to do this is to set the frequency manually triggering by a userspace application by using the CPUfreq sysfs interface:
echo userspace > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
Then see all the available operating points:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
and set the greatest available frequency (it should be 1 GHz)
echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/ scaling_setspeed
There ia an other possible way for changing the frequency by looking at the .../kernel//arch/arm/mach-omap2/clock3xxx_data.c file and search for where is set the core_ck.rate. You could pay attention to the code below the comment: /* DPLL3 output M2 - primary control point for CORE speed */. The way for setting the code speed seems very complex and not tested by me.
BR
Tsvetolin Shulev