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DMA in FIFO mode on an 8148

Bernard Seller
Intellectual 530 points

I am trying to DMA from a  GPMC attached FPGA (NOR - like) on an 8148 processor to memory

using the FIFO mode for FPGA

I modified the edma_test example and it runs fine in the INCR mode for edma_set_src

but if I change the mode to FIFO instead the DMA never completes ....

I am surely missing a little configuration detail in the GPMC or the edmacc_param or something

Could someone point me to a working example of the FIFO mode for the 8148

thanks

Bernard

  • 0
    TI__Guru**** 170625 points

    Hi Bernard,

    So, in your use-case the source is the GPMC attached FPGA/NOR and the destination is the DDR3 SDRAM memory, is that correct? And your EDMA transfer works fine when set to INCR mode (both source and destination) and does not work when set source to Constant/FIFO mode and destination to INCR mode, is that the case?

    Are you working with EZSDK 5.05.02.00?

    Best Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 530 points

    Yes your interpretation of what I am doing is correct

    SDK :   R4 SP2

    Kernel : Linux dm814x-evm 2.6.37

    (for now, we are stuck with an older environment due to other dependencies)

    thanks

    Bernard

  • 0 in reply to Bernard Seller
    TI__Guru**** 170625 points

    Bernard,

    Bernard Seller said:
    SDK :   R4 SP2

    I am not sure what is this SDK. We have EZSDK, DVR RDK, IPNC RDK for DM814x.

    Anyway the SDK is not so important for your specific question.

    What is the source address you have set? As you are using NOR-like memory, I assume you are not using the pre-fetch engine FIFO for your EDMA transfer, is that correct (as it is for NAND)?

    In your specific FPGA/NOR device, do you have hardware buffer (FIFO) which maps to a single shift register, thus when reading (in constant mode) this register, every read cycle make it automatically shift to the next location in the hardware buffer (FIFO)?

    The specific requirements for the constant/FIFO EDMA mode are documented in the DM814x TRM:

    8.2 Features
    The EDMA3 transfer controller has the following features:
    Support for increment or constant addressing mode transfers. - this means you should use increment OR constant/FIFO addressing mode, you can not use both for the same source. As you successfully use increment mode, I would expect your source (FPGA/NOR) is designed/suitable for this mode, and constant/FIFO mode can not be used.


    OPT[10:8] FWID - FIFO width. Applies if either SAM or DAM is set to constant addressing mode.


    OPT[0] SAM = 1 Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching FIFO width.

    8.4.3.8 Constant Addressing Mode Transfers/Alignment Issues

    If either SAM or DAM is set (constant addressing mode), then the source or destination address must be aligned to a 256-bit aligned address, respectively, and the corresponding BIDX should be an even multiple of 32 bytes (256 bits). The EDMA3CC does not recognize errors here, but the EDMA3TC asserts an error if this is not true. See Section 8.4.12.3.

    NOTE:
    The constant addressing (CONST) mode has limited applicability. The EDMA3 should be     configured for the constant addressing mode (SAM/DAM = 1) only if the transfer source or destination (on-chip memory, off-chip memory controllers, slave peripherals) support the constant addressing mode. See the device-specific data manual and/or peripheral user`s guide to verify if the constant addressing mode is supported. If the constant addressing mode is not supported, the similar logical transfer can be achieved using the increment (INCR) mode (SAM/DAM =0) by appropriately programming the count and indices values.

    Regards,
    Pavel