How can I disable ARM RAM/ROM in PSC0?

Hi,

At which/what area of code that You are trying to disable ARM RAM/ROM module(LPSC #7) in PSC0 ?

like gel file or AISgen tool .cfg or any application code or ARM UBL code,

Hi,

Refer this code for disable/enable LPSC#7 and this code can be used in gel file.

/*PSC Module Related Registers*/
#define PSC0_BASE       0x01C10000
#define PSC1_BASE       0x01E27000

#define PSC0_MDCTL      (PSC0_BASE+0xA00)
#define PSC0_MDSTAT     (PSC0_BASE+0x800)
#define PSC0_PTCMD      *(unsigned int*) (PSC0_BASE + 0x120)
#define PSC0_PTSTAT     *(unsigned int*) (PSC0_BASE + 0x128)
#define PSC_TIMEOUT      200

#define LPSC_ARM_RAMROM  7   /*PSC0*/


/*Enable Function for PSC0*/
PSC0_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;

    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC0_PTCMD = 0x1<<PD;

      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }

      j = 0;
      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}


/*Disable Function for PSC0*/
PSC0_LPSC_disable(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;

    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x2 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0002;
      PSC0_PTCMD = 0x1<<PD;

      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }

      j = 0;
      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x2) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}

PSC0_LPSC_disable(0, LPSC_ARM_RAMROM);
PSC0_LPSC_enable(0, LPSC_ARM_RAMROM);

Hi Titus,

Thank you for sending the GEL code.

I tried it on omap-l138 evm, but I could not disable the ARM RAM/ROM module.

Is there any other procedure to disable the module?
Your cooperation would be highly appreciated.

Best regards,
j-breeze

Hi Titus,

I've got the messages below that mean module state transition was failed.

  " C674X_0: Output:    PSC0 Enable Verify Timeout on Domain 0, LPSC 7 "

  " ARM9_0: Output:     PSC0 Enable Verify Timeout on Domain 0, LPSC 7"

Any comments would be appreciated.

Best regards,
j-breeze

Hi Breeze,

Sorry,

I will try to reproduce this and will update on monday.

Hi J-Breeze

Can I ask why are you trying to disable the ARM RAM / ROM. The power savings from this will be less then ~ 5 mW and could be lower if you are running at lower CVDD.

Disabling a peripheral clock via PSC implies that you have to absolutely make sure that there are no accesses to that peripheral. If any state machine within the module is active, the module will not acknowledge the clock stop request and will not allow PSC to clock gate the peripheral.

For a RAM it is even more trickly as apart from data accesses you have to make sure that program accesses are not happening also. Assuming you are doing this post boot, ROM should not be in the mix, but it is possible that there is code in the RAM that is being accessed etc, that is disallowing the RAM to be clock gated.

Again, the power savings are not enough, so perhaps you do not need to explore this feature.

Regards

Mukul 

Titus,

Thank you for your help, and I am sorry I did not notice that.

Best regards,
j-breeze