• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Subscribers 100 subscribers
  • Views 1336 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCIe Memory Read problem whit BOC

kchakechk zakaria
Intellectual 460 points

Hello,

I'm using PCIe interface of C6678 DSP , for communication between two DSP "RC to EP" whit the CI2EVM_BoC dual evm interface card, I use the code PCIEexampleProject by TI. I realized a number of scenarios like Memry read and memory write with/without   common REFCLK " is generated on the BoC".

But now I tried to create a new scenario :

* RC  write data to EP

* RC Read the same data from

this scenario without common REFCLK Mrd and Mwr  is OK

but with common REFCLK just MWr is OK and MRd is NOTOK

my scrbuf[i]=i (RC)  but I find that in dstbuf(RC)

the results:

I really need to work wtih common REFCLK, help plz,

 

Regards,

Zakaria.

  • 0
    TI__Mastermind 28085 points

    Hi Zakaria,

    How do you select common REFCLK mode on your test? Have you modified jumper setting in BOC(Break out card) and EVMs.

    In common REFCLK mode Mwr is working means both side PCIe links are up.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi, thanks for your reply.

    How do you select common REFCLK mode on your test? Have you modified jumper setting in BOC(Break out card) and EVMs.

    - I remove the shunt from JP3 and JP10 to enable common REFCLK

    - I set  SW5[3] ans SW9[2]

    ==> the test MWr only with common REFCLK is OK

    ==> MRd only with common REFCLK is also OK

     

    but in this scenario :                   

                                  * RC  write data to EP

                                  * RC Read the same data from

    ==> the transaction MWr with common REFCLK is OK

    ==> MRd only with common REFCLK is NOT OK

    the result exactly:

    **********************************************

    *             PCIe Test Start                *

    *                RC mode                     *

    **********************************************

     

    Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Mar 19 2014:12:10:35

     

    FPGA reset status reg = 0x000000f7

    PCIESSEN state is = 0x00000001 : PCIE ENABLED

    User SW state is = 0x00000001

    ICS557_SEL currently drives = 0x00000001

    Changing ICS557_SEL to 'drive high' (PCIe_ref_clk - ext)

    PCIe Power Up.

    PLL configured.

    Successfully configured Outbound Translation region 0!

    Starting link training...

    **********************************************

    *             PCIe Test Start                *

    ICS557_SEL updated drives = 0x00000001

    *                EP mode                     *

    **********************************************

     

    Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Mar 19 2014:12:39:05

     

    FPGA reset status reg = 0x000000f7

    PCIESSEN state is = 0x00000001 : PCIE ENABLED

    User SW state is = 0x00000001

    ICS557_SEL currently drives = 0x00000001

    Changing ICS557_SEL to 'drive high' (PCIe_ref_clk - ext)

    ICS557_SEL updated drives = 0x00000001

    PCIe Power Up.

    PLL configured.

    Successfully configured Inbound Translation!

    Starting link training...

    Link is up #EP.

    EP is Ready

    Link is up #RC.

     RC send data to EP using CPU

     RC received from to EP using CPU

    Regards, Zakaria

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Zakaria,

    yes your jumper settings are correct for common REFCLK mode, i think S5.3 selection is valid at PCIe boot mode.

    Are you using TI provide "PCIE_exampleProject" or customized code. if you using customized code please share the code, i reproduce the issue and let me know the possible solution.

    In "PCIE_exampleProject" RC write the data to EP, EP receive the data and write the same data to RC. RC receive the data from EP and verify the dstBuf and srcBuf. this example code does not have read function.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi,

    I based on the code provide by TI but I made more modifications,

    My projects : 2100.workspace_v5_3.rar

    he works very good without common refclk, but with common REFCLK I have the same problem.

    Regards,

    Zakaria,

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Zakaria,

    In common REFCLK mode you told RC write data to EP memory successfully, you verify/debug the data is correctly received in EP side.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi, thanks for your reply again.

    yes exactly I have this problem sometimes at the writing to EP, I found just the 0....

    But why this problem when used common REFCLK.

    What can I do? this is a problem  setting in BOC or in EVMs or something else?

     

     

    Regards,

    Zakaria,

     

  • 0 in reply to kchakechk zakaria
    TI__Genius 12065 points

    Zakaria,

    Are you saying there is issue for both MemWrite and MemRead when using common ref clock please?

    Could you check the following registers on both RC and EP sides when you observe the issue please?

    - DEVSTAT (0x02620020) -- especially PCIESSMODE[1:0] to see if one EVM is RC and another one is EP

    - PCIE_SERDES_CFGPLL (0x02620358) -- if multipler matches ref clock frequency (0x1c9 matches 100MHz)

    - PCIE_SERDES_STS (0x0262015C) -- if LOCK field is 1 to indicate PLL is locked

    - DEBUG0 (0x21801728) -- LTSSM_STATE=0x11 to indicate link is up 

    - CMD_STATUS (0x21800004) -- if IB_XTL_EN is enabled on EP and OB_XLT_EN is enabled on RC

    On RC side:

    - OB_OFFSET_INDEX0 (0x21800200)

    - OB_OFFSET0_HI (0x21800204) 

    On EP side:

    - IB_BAR0 (0x21800300)

    - IB_START0_LO (0x21800304)

    - IB_START0_HI (0x21800308)

    - IB_OFFSET0 (0x2180030c)

    - BAR1 (0x21801014)

      -- see if RC outbound translations match with EP inbound translations

     

     

     

  • 0 in reply to Steven Ji
    Intellectual 460 points

    Hi Steven , thanks for your reply

    I repeated the test again and I found:

    DEVSTAT (0x02620020) -- especially PCIESSMODE[1:0]  EP(0001080B)  RC(0001880B) IS OK

    - PCIE_SERDES_CFGPLL (0x02620358) ==> yes 000001C9

    - PCIE_SERDES_STS (0x0262015C) -- if LOCK field is 1 to indicate PLL is locked  is  OK  (00000209)

    - DEBUG0 (0x21801728)  EP(00004600) RC (00006700)

    - CMD_STATUS (0x21800004) -- if IB_XTL_EN is enabled on EP  is  OK and OB_XLT_EN is enabled on RC is OK 

    .

    On RC side:

    - OB_OFFSET_INDEX0 (0x21800200)   = 70000001

    - OB_OFFSET0_HI (0x21800204)  = 00000000

    On EP side:

    - IB_BAR0 (0x21800300)  = 00000001

    - IB_START0_LO (0x21800304) = 70000000

    - IB_START0_HI (0x21800308) = 00000000

    - IB_OFFSET0 (0x2180030c)  =  0C000000

    - BAR1 (0x21801014) = 70000000

    ==> RC outbound translations (70000000) match with EP inbound translations (70000000) 

     

    Regards,

    Zakaria,

     

  • 0 in reply to kchakechk zakaria
    TI__Genius 12065 points

    Zakaria,

    If LTSSM_STAT=0x00 in DEBUG0, it means the link is DOWN and the data transfer could not happen as you observed.

    I am not sure if the link is down when you do the data transfer or the link is never up. So you might want to monitor DEBUG0 before the data transfer as well and see if link will be up all the time and what could trigger the link down. 

    PCIE_SERDES_STS shows LOSDTCT1 (bit9) and LOSDTCT0 (bit3) are being set, which means there is loss of signal detected on both lanes. Maybe you would like to check PCIe ref clock input from BOC (A_PCIE_REF_CLK_P/N, B_PCIE_REF_CLK_P/N) to see if there is valid 100MHz provided from BOC, even though LOCK is being set.

    And I think you only need common PCIe ref clock from BOC (remove J3 shunt), right? Why you remove J10 shunt as well please? Do you want to provide common Main PLL ref clock to both EVMs? If so, please check your main PLL input clock and see if the frequency matches your PLL configuration programming. 

  • 0 in reply to Steven Ji
    Intellectual 460 points

    Steven,

    yes for JP10 is shunted now I remove the shunt just for JP3 to activate the PCIECLK Source, but how i can check PCIe ref clock input from BOC (A_PCIE_REF_CLK_P/N, B_PCIE_REF_CLK_P/N)??

    thanks, 

    Zakaria,

  • 0 in reply to kchakechk zakaria
    TI__Genius 12065 points

    Zakaria,

    I think BOC user guide has the schematic of clock signals such as U17 pin 10/11 and 14/15.

    You can also check the input/output pins of U1 on C6678 EVM, which is the clock mux of PCIe ref clock. The EVM schematic PDF should have the pin/signal names.