How to set video timings for DVRRDK-04.01.00.02 u-boot?

Hi,

In addition to VENC frame size, you will need to change the GRPX frame size also, the default frame size is 640x480, change WIDTH and HEIGHT macro to 1920x1080 or 1280x720.

Enable internal color bar to make sure that the timing information is correct. 15th bit of the cfg0 register is used to enable internal color bar.

Rgds,

Brijesh

Hi,

I tried internal color bar, the screen is always  right.

Q1. I am change Venc h_front_porch from 88 to 256 as below, then the screen does not flicker/ flash..

From : configVenc(0x6000, 0x2, argv[0], 1920,  88, 148,  44, 1080, 4, 36, 5);

To : configVenc(0x6000, 0x2, argv[0], 1920,  256, 148,  44, 1080, 4, 36, 5); >> but this is inconsistent with the specification

Q2. I make sure WIDTH and HEIGHT that are correct, but shift is always there.

Q3. How to set the pixel clock (148500 or 74250) to cup register, the u-boot do not description this?

{ VDIS_TIMINGS_1080P_60, 148500, 1920, 88, 148,  44, 1080, 4, 36, 5 }

{ VDIS_TIMINGS_720P_60,   74250, 1280, 110, 220,  40,  720, 5, 20, 5}

Thanks a lot.

Hi,

Changing the timing information is not the good way, it may fail when you connect to display device which strickly follows CEA standards.

If you are seeing internal color bar correctly and your display device is detecting incoming resolution correctly, your timing information and pclk settings are correct, you just have to look into the input grpx pipeline settings. I think the problem is in the grpx pipe line settings only. Can you check if grpx pipeline is getting configured with the correct frame size and correct position? Grpx can be configured with the small frame size and it could be positioned in the output frame. There is some function like create_data_descriptor, this is where it will configure grpx pipeline. Have a look into this function.

Rgds,

Brijesh

Hi Brijesh,

I can not fint create_data_descriptor and what is the meaning of grpx pipeline?

Is Grpx pipeline ti816x_dispmgr_create_grpx_conf_descriptor or ti816x_dispmgr_setup_layers APIs in u-boot? or others?

I check the u-u-boot code as below,

/* HDMI->VGA Configuration Desc:GRPX0 */
size = ti816x_dispmgr_create_grpx_conf_descriptor(0, list_addr, payload_buffer, 1920, 1080);
ti816x_vpdma_send_list(list_addr, size, 0);
/* wait for list complete interrupt */
if ( ti816x_dispmgr_wait_for_list_complete(1) == -1 ) {
    return -1;
}

vpdma_write32(VPDMA_GRPX0_DATA_CSTAT, 0x00000000);

/* DATA Descriptors for HDMI/VGA */
size = ti816x_dispmgr_setup_layers(list_addr, 3*1920, 1920,1080, disp_time, disp_fps, paddr);
ti816x_vpdma_send_list(list_addr, size, VPDMA_LIST_NUMBER_HD);
while ( ti816x_dispmgr_wait_for_list_complete(1) == -1 );

u32 ti816x_dispmgr_create_grpx_conf_descriptor(
                        s32   grpx_unit,
                        u32 * desc_buffer,
                        u32 * payload_buffer,
                        u32   xres,
                        u32   yres)
{
    u32   size    = 0;
    u32 * desc    = NULL;
    u32 * payload = NULL;


    /* Set up frame configuration descriptor. */
    desc = desc_buffer;
    desc[0] = 0x1;                  /* frame configuration address */
    desc[1] = 16;                   /* data length */
    desc[2] = (u32)payload_buffer;  /* payload location */
    desc[3] = 0
        | (0xB<<27)                 /* packet type */
        | (0<<26)                   /* indirect command */
        | (1<<24)                   /* block type */
        | ((grpx_unit+1)<<16)       /* destination GRPX0..GRPX2 */
        | (1<<0);                   /* payload size in 128 bit units */


    size += 16;

    payload = payload_buffer;
    payload[0] = 0;         /* reserved */

    payload[1] = 0
            | (xres<<16)    /* frame width */
            | (yres<<0);    /* frame height */

    payload[2] = 0;         /* reserved */
    payload[3] = 0
        | (0<<30)           /* progressive format */
        | (1<<31);          /* yes soft reset of GRPX unit */

    return size;
}

static u32 ti816x_dispmgr_setup_layers(
                        u32 * desc_buffer,
                        s32   stride,
                        s32   width,
                        s32   height,
                        u32   dispTime,
                        u32   dispFps,
                        u32   paddr)
{
    u32   size = 0;
    u32   numDesc = 0, i = 0;
    u32 * desc = NULL;
    s32   chan = 0;
    s32   x = 0;
    s32   y = 0;
    u32   layer_ctrl = 0;


    desc = desc_buffer;

    layer_ctrl = 0x0000E400;


    /*
     * Set up data descriptors for GRPX units.
     */
    /* add src_viewport origin to surface start address */
    layer_ctrl |= 1 << (2);  /* enable GRPXx layer */

    chan = GRPX0_CHANNEL_NUMBER;

    /*
     * Program the same data descriptor
     *  DISPLAY_TIME_IN_SECS x DISPLAY_FPS times.
     *
     * Buffer size for descriptors is VPDMA_DESC_BUFFER_SIZE.
     *  If size needed for descriptors is more than this
     *  then limit number of descriptors to fit within
     *  VPDMA_DESC_BUFFER_SIZE
     */
    numDesc = dispTime * dispFps;

    if ( numDesc * VPDMA_DATA_DESC_SIZE > VPDMA_DESC_BUFFER_SIZE) {
        numDesc = VPDMA_DESC_BUFFER_SIZE / VPDMA_DATA_DESC_SIZE;
    }

    for ( i = 0; i < numDesc; i++ ) {

        /* set up data transfer descriptor */
        desc[0] = 0
            | (DATA_TYPE<<26)    // RGB-888
            | (0<<25)            // no notification
            | (0<<24)            // field number
            | (0<<23)            // 2-dimensional data
            | (0<<20)            // +1 line skip (even)
            | (0<<16)            // +1 line skip (odd)
            | (stride);          // line stride

        desc[1] = 0
            | (width<<16)        // line length in pixels
            | (height);          // number of rows

        desc[2] = paddr;

        desc[3] = 0
            | (0xA<<27)         // packet type
            | (0<<26)           // 1D mode
            | (0<<25)           // inbound direction
            | (chan<<16)        // channel
            | (0<<9)            // priority
            | (chan<<0);        // next channel

        desc[4] = 0
            | (width<<16)       // region width
            | (height);         // region height

        desc[5] = 0
            | (x<<16)           // horizontal start
            | (y<<0);           // vertical start

        desc[6] = 0
            | (1<<7)            // first region
            | (1<<8);           // last region

        desc[7] = 0;            // alpha blending enable
        desc += 8;
        size += 32;
    }

    /* enable GRPX on both HDMI and HDCOMP */
    vps_write32(VPS_COMP_HDMI_VOUT1, layer_ctrl);

    vps_write32(VPS_COMP_HDCOMP, layer_ctrl);

    return size;

}

BR, Charles

Please make sure that the size is correct inside create_grpx_conf_descriptor and setup_layers api. Even in create_grpx_conf_descriptor_dvo2/hdmi/sd and setup_layers_dvor/hdmi/sd apis.

Rgds,

Brijesh

I make sure that the size is correct, so i don't know what's happened.

Have any sample code with 1080p, let me refer?

Thanks.

Hi,

You could search on the forum, there are many people who are able to get boot logo working for different resolution.

Rgds,

Brijesh

Hi,

I did not find the relevant settings from the forum.

I borrowed a DVR device and dump cpu version 0x48140600 using get_cpu_rev API base on u-bbot.

The CPU vesion is 1, and the display resolution is work on 1080p.

But Our ARM 3894 & DM816X CPU version is 3, the display resolution only work on 640*480@60 normal.

So, how to solve the issue for others resolution on CPU version 3?

Hi Lin,

Version 3 is latest revision, so same changes should work even on revision 3. I think you are trying on on-chip hdmi correct. Can you enable internal color bar and see if it works fine? You could enable internal color bar by setting 15th bit at the offset 0x48106000. If color bar works fine, timing is correct, you will just have to look into the graphics parameters.

Rgds,

Brijesh