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DDR3 Routing DQn and DQS_N/P clock on different layers

Mads Holmer
Prodigy 50 points

Other Parts Discussed in Thread: TMS320C6655

Hi all,

Based on TI Eval board TMDSEVM6657L design, I have at design with:

DSP TMS320C6655 and 3 x DDR3 RAM Micron MT41J128M16HA-125

12 layer PCB with GND as reference for all signal layers. All layer with impedance specification and traces routed as 50+/-10% ohm and differential pair as 100 ohm.

In app notes I found that 'It is recommended that the differential clock signals be slightly longer than the control and address lines – this is due to the fact that differential signals have an inherently faster propagation time than the single-ended address and control pins' 

What is slightly longer ?

Do the same apply to the DQS_N/P signals they are also routed as differential pair ?

I am struggling about the layout for each byte-lane, to match the length, anybody having experience to route the DQS_N/P signals on other layer than the associated DQn signals ?

What about relation between the 4 (5) byte lanes, should they be equal length ?

Any comments will be highly appreciated.  

 

  • 0
    TI__Mastermind 42545 points

    Hi Mads,

    The clock, address and command signals must still be routed with the length matching requirements listed in the DDR3 Design Requirements for KeyStone devices. That document states that the length of all address and command signals from the SOC to the memory device should be within +/-20mil of clock trace length. The app note states that it's better practice to keep the address and command traces between the length of the clock to 20mil less than that length. 

    The length matching between the DQSP/N, DQM and the DQ lines is the tighter +/-10mil. Although the same principle applies, the tighter length matching should compensate a longer DQSP/N length. As long as all the signals are within the +/-10mil, you should be fine.

    We recommend all eleven signals for a byte lane be routed on the same layer. This eliminates the concern for the via barrel portion of the length matching since it is the same for each signal. 

    Each of the eleven signals within a byte lane must be length matched but the lengths from one byte lane to the next do not have to match. For example, the DQS0P/N, DQ0-7 and DQM0 of the C6657 EVM are length matched to around 1264mil while the DQS2P/N, DQ16-23 and DQM2 are length matched to 1173mil. The leveling process will compensate for the length of each byte lane.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 50 points

    Hi Bill,

    Thank you for feedback on my questions, it have been very helpful.

    I have almost finished the design and layout of the board now, full control over each byte-lane data etc.

    But the routing and length matching of the address lines have raised a question. What about the length of the via barrel ? I have address lines in layer L3, L5. L8 and L10. Layer L1 to L3 distance 0.183mm and Layer L1 to L10 distance 1.178mm. This result in a difference in travel length of approx 2mm -> 14 pS

    The document states that the length of all address and command signals from the SOC to the memory device should be within +/-20mil of clock trace length.

    The Cad-tool only calculate the routing length, should the length of barrel portion be manual compensated ?

    Do I need to anything or just order the PCB.

    Thanks in advance.

    Best regards

    Mads Holmer

  • 0 in reply to Mads Holmer
    TI__Mastermind 42545 points

    Hi Mads,

    The number of address and command lines make it impossible to route them on the same layer. Fortunately, these signals are actually transitioning at half the speed of the data lanes so there is additional slack available in the timing. The trace length matching numbers provided recognize that the signals will be routed on different layers and that the via barrel lengths will be different. Matching the trace length without including the via barrels should be sufficient. Remember that you are matching the trace length from the the SOC to the memory individually for each memory device. The stubs between the fly-by trace and the ball of the memory should be kept as short as possible as well. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 50 points

    Hi Bill,

    Once again, thank you for the fast and detailed response. I will then go on....

    Regards, Mads