TI Experts-
Our board has a NAND Flash device with 8x the capacity of the one on the EVM 6678 board. I've read through this thread:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/178889.aspx
and I think we may not be able to use our current device as its requires an ECC calculate rate of 4-bits up to 528 bytes, and the 6678 NAND controller supports 4-bits up to 512 bytes. My questions:
1) As a temporary measure, until we change our board design, is it possible to configure our device with identical page size as the EVM, but define more spare bytes per page? For example, in our case we would have 1600 bytes (out of 2112 total bytes per page) defined as spare / not used. In platform library NAND driver definitions, we would correctly set pages per block, blocks per device, and we would maintain all ECC constants.
2) Since ECC structure / support seems to be the main obstacle, would you recommend using a NAND Flash device with internal ECC support and then disabling ECC in the 6678 NAND controller? Is this possible?
3) Is there a high capacity NAND Flash device that you can recommend for new 6678 designs?
Thanks.
-Jeff
Signalogic