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C6748 SPI Slave Boot Mode

Gonzalo R.
Intellectual 310 points


Hi all,

I'm trying to boot a C6748 DSP configured in slave SPI boot mode. During SWS or POS I will have to read from DSP in order to check if my synchronization is alright, for which I will have to set the SPI Clock on to capture  my DSP's response.

Being that clock engaged, I am concerned that the DSP will continue to capture information through the MOSI line and confuse it with some new opcode or argument.

Is this going to happen, or is DSPS's MOSI input disabled during MISO reading? How can I avoide that if it is happenning that way?

Thanks a lot,

Gonzalo

  • 0
    TI__Mastermind 43955 points

    Hi Gonzalo,

    Gonzalo says said:
    Being that clock engaged, I am concerned that the DSP will continue to capture information through the MOSI line and confuse it with some new opcode or argument.

    During SWS, POS and OS,  each stage will happen one after the (successful completion of the) other.

    Where is the chance to get confused with new opcode? provided each recv opcode is sent from the slave as an acknowledgement during POS and OS. Do you mean to ask, in-between the POS and OS?

    We do not understand what you meant by "Being that clock engaged".

    In the SPI-boot modes, the received data is sampled at the rising edge of the clock and the data to be

    transmitted on the falling edge of the clock.

    As per the wiki below, in additon to SPICLK, SPISIMO, SPISOMI, SPICS have also to be connected between the host and the DSP.

    and the clock phase diagram is also given there.

    http://processors.wiki.ti.com/index.php/Using_the_D800K001_bootloader_in_SPI_Slave_mode#Boot_Requirements.2C_Hardware_Setup_and_Default_Settings 

    http://www.ti.com/lit/an/spraat2f/spraat2f.pdf

    please revert  if have any further questions.

     

    Regards,

    Shankari

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  • 0 in reply to Shankari G
    Intellectual 310 points

    Shankari G said:
    We do not understand what you meant by "Being that clock engaged".

    Hi Shankari, thanks for your reply,

    What I mean with that expression is that I want to be sure that the sampling phase is stopped while DSP is transmitting data to the Master and it will not take whatever is in that moment on SPISIMO as new data transmitted by the Master.

    Thank you very much,

    Gonzalo