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EVMK2H u-boot from MSMC RAM with CCS fails

On the EVMK2H, I tried to load and start u-boot from MSMC RAM using CCS and the JTAG emulator connection. I followed the directions in the MCSDK User Guide Exploring chapter:

http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Running_U-Boot.2C_Boot_Monitor_and_Linux_Kernel_on_EVM

It gets as far as displaying the following messages and then hangs:

U-Boot 2013.01 (Dec 30 2013 - 13:19:04)

I2C:   ready
Detected SO-DIMM []
DRAM:  2 GiB

Note that these are the same messages I get when booting normally (but, of course, it goes on). When I stop the emulator, the SP is suspiciously set to "0x0BADCODE" and the PC is at 0x0C001010. The program is then in a 3-instruction loop c001010->c0012c0->c0012c4.

I left the switch on the EVM for SPI boot (0010), but I did a CPU reset before I started. I also tried this with the DSP NOBOOT setting (0001) and did not even get the messages shown above.

Note that I am not rebuilding u-boot when I do this, so it is still built as though loaded from a SPL in SPI NOR. Does that matter?

Is it even possible to boot the board this way? If not, how would I recover if the SPI flash got corrupted?

The EVM revision is 3.0 and the silicon revision is 1.1 (JTAG ID of 0x1b98102f).

Thanks,

Lance

  • Hi Lance,

    I have tried same procedure in revision 3.0 board. I am able to succeed and getting u-boot prompt.

    I have used pre-built u-boot binary that comes along with MCSDK 3.0. 

    Please ensure to use the pre-built binary from MCSDK. We could see that the u-boot date is different in your log.

    Thanks.

  • Rajasekaran,

    I tried with the original image I got in the MCSDK download. I get the same results:

    U-Boot 2013.01 (Nov 24 2013 - 16:43:18)
    
    I2C:   ready
    Detected SO-DIMM []
    DRAM:  2 GiB
    

    However, since the posting, I have gotten it to boot, but I don't know why. It will complete u-boot booting if I have allowed the board to boot normally (without the emulator) from SPI NOR. However, if I start the board in NOBOOT mode (DIP switch 0001) and do the emulator boot procedure, it does as reported earlier -- boots only up to reporting the DRAM size and then hanging.

    Since the u-boot image I am booting via the emulator (/opt/ti/mcsdk_linux_3_00_03_15/images.orig/u-boot-keystone-evm.bin) is what is normally loaded by the u-boot SPL, is it possible that some necessary SPL initialization is not being done if the SPI NOR program does not run?

    Note that there is no initialization script being run by evmk2h.ccxml. Should there be?

    Is there a different u-boot image I should be booting in the case of emulator boot?

    My goal is to be able to recover a system that has had all NV memory wiped out (or to initialize a new system that has never had any NV memory programmed). So I cannot count on anything in the SPI NOR.

    Thanks,

    Lance

  • Hi Lance,

    You should follow below wiki steps with "No boot" mode 0001.

    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Running_U-Boot.2C_Boot_Monitor_and_Linux_Kernel_on_EVM

    Q: Note that there is no initialization script being run by evmk2h.ccxml. Should there be?

    No Init script required.

    Q: Is there a different u-boot image I should be booting in the case of emulator boot?

    No.

    I have some questions and suggestions.

    1. Are you able to boot with "SPI NOR boot" mode 0010?

    If yes, Please provide complete u-boot log.

    2. From your log, I suspect there may be problem with DDR DIMM installation on your EVM. Please ensure it is mounted right & tight.

    3. The u-boot log will have the DDR DIM part number. Please refer the example log below.

    I2C:   ready
    Detected SO-DIMM [18KSF1G72HZ-1G6E2 ]
    DRAM:  Capacity 8 GiB (includes reported below)
    DRAM:  2 GiB
    NAND:  512 MiB
    Net:   TCI6638_EMAC, TCI6638_EMAC1

    Thanks.

  • Rajasekaran,

    The EVM has never failed to boot from SPI NOR (i.e., without using the emulator). However it also never gives a name for the SO-DIMM.

    When I remove the SO-DIMM, I get an error and it hangs:

    U-Boot 2013.01 (Nov 24 2013 - 16:43:18)
    
    I2C:   ready
    Cannot read DIMM params
    Detected SO-DIMM []
    

    But with the DIMM installed, it boots fine. Below is the u-boot output with the SO-DIMM installed booting directly from SPI NOR (I cut it off during kernel boot, but that always works as well):

    U-Boot SPL 2013.01 (Nov 24 2013 - 16:43:18)
    SF: Detected N25Q128A with page size 64 KiB, total 16 MiB
    
    
    U-Boot 2013.01 (Nov 24 2013 - 16:43:18)
    
    I2C:   ready
    Detected SO-DIMM []
    DRAM:  2 GiB
    NAND:  512 MiB
    Net:   TCI6638_EMAC, TCI6638_EMAC1
    Hit any key to stop autoboot:  0
    BOOTP broadcast 1
    BOOTP broadcast 2
    BOOTP broadcast 3
    DHCP client bound to address 172.22.12.59
    Using TCI6638_EMAC device
    TFTP from server 172.22.12.93; our IP address is 172.22.12.59
    Filename '//uImage-k2hk-evm.dtb'.
    Load address: 0x87000000
    Loading: ####
             941.4 KiB/s
    done
    Bytes transferred = 57857 (e201 hex)
    BOOTP broadcast 1
    BOOTP broadcast 2
    DHCP client bound to address 172.22.12.59
    Using TCI6638_EMAC device
    TFTP from server 172.22.12.93; our IP address is 172.22.12.59
    Filename '//skern-keystone-evm.bin'.
    Load address: 0xc5f0000
    Loading: ####
             879.9 KiB/s
    done
    Bytes transferred = 45056 (b000 hex)
    BOOTP broadcast 1
    DHCP client bound to address 172.22.12.59
    Using TCI6638_EMAC device
    TFTP from server 172.22.12.93; our IP address is 172.22.12.59
    Filename '//uImage-keystone-evm.bin'.
    Load address: 0x88000000
    Loading: #################################################################

    I looked at init_ddr3 in ddr3.c (u-boot) and the name is checked against the one you show in your log. If it matches, then it configures at 400MHz, otherwise it uses 333MHz.

    The SO-DIMM on my board is marked as 2GB and has an Advantech sticker on it.

    I also notice that your log shows a total of 8GiB while mine only show 2GiB. Is yours the same board type as mine (Advantech K2-EVM-HK)?

    Thanks,

    Lance

  • Hi Lance,

    I don't have any idea about this issue since I am unable to reproduce it.

    Let us compare other dependencies which may require to solve the issue.

    Below is my configuration:

    1.  CCS v 5.5 

    2. Ubuntu 12.04 LTS

    3. MCSDK 3.00.03.15

    Thankss.

  • Rajasekaran,

    Your software configuration matches mine.

    From our earlier discussion about the DIMM, I have 2GB, 333MHz and you appear to have a 8GB 400MHz. Could that be significant?

    Perhaps I should use the emulator to see if I can capture where it fails. I tried this before without much success.


    Thanks,


    Lance

  • Rajasekaran,

    I found something that seems to work. I had been doing a "CPU Reset (SW)" before doing the loadJSFile and run steps. This morning, I tried (from power on) not doing that reset and it worked.Then I tried doing a "System Reset" and no CPU Reset and it worked.

    I did a series of experiments and found that it always fails if I do a CPU Reset before load/run and it always works if I do a System Reset and no CPU Reset before load/run. If I do a System Reset followed by a CPU Reset, then the load/run fails.

    So, I am not sure why it is, but a CPU Reset always seems to result in a failed load/run. Perhaps you can explain why, but, in any case, I have something that works.

    Thanks,

    Lance

  • Hi Lance,

    I am glad that you are able to run successfully. From my understanding, no need to do any reset before running script. 

    System Reset – This reset will typically reset the the entire device. In multi-core devices all cores are reset.

    CPU Reset – Typically isolated to reset just the core, not the entire device. In multi-core devices typically isolated to a single core. In devices that support a software reset, a CCS Reset may be equivalent.

    http://processors.wiki.ti.com/index.php/Emulation_Resets

    If you have any queries on CCS reset, please post on CCS forum.

    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/154424.aspx

    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/31886.aspx

    Thanks.