dma channels sharing pci trouble

Dear Guy,

Can you please tell more abt your 2 DMAs?.  I think  there will be one DMA in that it may have 2 or 4 TCs, and  some logical channels ( 8 or 16 or 64) you can map these logical channels on TCs. So if you are using two different TCs to have parallel transfer, make sure there is no conflict between shared resources ( like PaRam etc).

Veeru, thank's for your interest.

I use the same TC for the 2 DMA transfer and channels are not shared by the these 2 DMA transfer.

Each transfer are between the DDR2 and the PCI. The L1 and L2 cache are enable. I take care of the invalidate with the cache.

I do some single pci access before the start of the chained transfer. So for now I'm not sure if the disturb of the linked transfer comes from the singles access or from the chained transfer.

Thank's again,

Guy

Typo miss: it's not DM6737 but DM6437... Sorry.

I upgrade TI drivers and the occurrence of the trouble falls from several miss per seconds to 1 miss per some seconds.

Their is my upgrade:

pspdriver: 1.10.01 -> 1.10.03

EDMA3_LLD: 1.05.00.01 -> 1.10.00

BIOS: 5.32.03 -> 5.33.06

Hi,

If the L1 and L2 cache is disable, the trouble of incomplete DMA transfer disappear. But I need it. I continue...

Again, any ideas are welcome.

Guy

If only the L2 is disable, the trouble is there but one time every few minutes.

Question:

If a PCI write EDMA transfer is started and, during this transfer a CPU single PCI write is done, is it a case of this errata ?

2.1.9 Data Corruption Possible When Multiple Masters Write to PCI Data Space or EDMA3 Transfer
and Channel Controller Registers (DM6437 and DM6433)

Extract of sprz250d.pdf