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a problem about SPI bootmode on c6678

The board is myselve's , which use C6678, the envirment is CCS5.3

when I use noboot mode, I can connect simulator and load program without problems, but when I write a program into flash(just a simple helloworld program and I use writting tools in MCSDK), then choose SPI mode, a problem named 1143 occured when I connect the simulator.

Now I have verified that the data in the flash is correct and, I can go through smoothly with another board which has nearly same design.

How should I do with it? Every suggestion is appreciative. 

  • I'm desired for the answer...

  • Fan Li,

    I will assume you mean the emulator and not the simulator. But I do not know specifically what you mean when you "connect the emulator". Do you mean physically reconnect it, or most likely you mean Connect Target?

    When the emulator does a Connect Target, it will automatically run one or more GEL scripts. In particular, the OnTargetConnect() and possibly OnReset() and OnRestart() GEL functions may execute.

    If your SPI is doing everything that it should be doing, then you should either remove the GEL file before doing the Target Connect operation, or edit your GEL file to comment out those automatic functions or their contents during this debug stage.

    Regards,
    RandyP

  • Hi Fan Li,

    We will need more information than what you have provided to help you with this issue.

    Can you please describe how your board is modelled. Is it similar to the EVM. Does it have a FPGA on board which runs firmware to redirect device to I2C EEPORM to run an IBL like primary boot loader as we do on the EVM. Are the reference clock used on the board same as EVM and what are your boot switch settings. What are the steps you have used to convert the out to a the boot table format  that you load on the SPI NOR.

    Have validated that your SPI boot image can be loaded on the EVM? It may be useful to validate this on the stable EVM before trying it on the custom board. Another effective way to debug is to connect to the device(without the GEL file) after the boot fails  and load and run the debug GEL file provided here.

    http://processors.wiki.ti.com/index.php/Keystone_Device_Architecture

    Please report the log and the PC value for us to analyze.

    Regards,

    Rahul

  • Hi Rahul Prabhu,

    We have already validated our SPI boot image on the stable EVM. Our own board's model is similar to the EVM's (we use the tools in MCSDK to convert the out to a dat) except some details:

    1.the reference clock is slightly different (we have tested that the clock is correct after it's stable).

    2.we don't use I2C EEPROM to run an IBL, we boot the board directly from the NOR FLASH.

    3.for swicth settings, we consult the TI bootloader manual. The value at the address 0x02620020 and 0x02320020  is 0x140d which is same as those on the EVM.

    4.we couldn't connect to the device any more after we reset the board (the boot  fails).

    We have tested the FLASH on another board and proved that it works well. And we have changed another DSP on our board but the boot also failed.

    What might be the cause of our problem? The matter is pressing, we hope that it would be dealt with as soon as possible.

    Thank you !!

  • Hi,

    What is the revision of silicon on your custom board. PG 1.0 is impacted by Advisory 8 which could lead to boot related issues due to incorrect initialization of PLLs. The value latched into DEVSTAT register appears to be correct.

    Can please run the debug GEL file provided here and provide us the log when the device boot fails. Ensure that you don`t use any gel file when you connect to the device initially after the boot fails then load and run the debug GEL script. It is important for us to understand the value of the Program counter and the state of the device when the boot fails to understand when the failure occurs.Also let us know if you see SPI transactions on the SPI lines after you power on the device?

    Regards,

    Rahul

     PS: Debug GEL file is provided on the wiki page below under debug section:

    http://processors.wiki.ti.com/index.php/Keystone_Device_Architecture