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AM3517 UART1 with CTS is not working

Kzk
Genius 5785 points

Hello,

I'd like to use UART1(ttyO0) with CTS, but uart1_tx send data while uart1_cts is de-asserted (level high). I also checked UART2(ttyO1) and UART3(ttyO2) with each CTS on J16 header pin of EVM3517 application board. These didnt send during de-asserted.  I mean the behavior of UART1 is not correct. I processed software with PSPv04.02.00.07 (Linux SDK v6) and BSL from Logic PD. Please give me advices.

Best Regards,

  • 0
    TI__Guru**** 393215 points

    Hi Kazu,

    Did you check that UART1 CTS is pinmuxed correctly?

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hi Biser

    Thank you for your quick reply. Yes, I think so. There is following description in BSL. I confirmed not only CONTROL_PADCONF_uart1_cts as default but also CONTROL_PADCONF_dss_data0 and CONTROL_PADCONF_mcbsp_clks.

    Regards,
    Kazu

    1016315A_AM35xx_BSL\bsl\src\evmam35xx_uart.c

    static const PIN_CONFIG  uart1_pin_mux[]={
       { CONTROL_PADCONF_uart1_tx,   MODE0,  PUPD_EN,  PULL_DOWN | INPUT_EN }, // uart1_tx
       { CONTROL_PADCONF_uart1_tx_HI,  MODE0,  PUPD_EN,  PULL_DOWN | INPUT_EN }, // uart1_rts
       { CONTROL_PADCONF_uart1_cts,   MODE0,  PUPD_EN,  PULL_DOWN | INPUT_EN }, // uart1_cts
    //   { CONTROL_PADCONF_dss_data0,   MODE2,  PUPD_EN,  PULL_DOWN | INPUT_EN }, // uart1_cts // TEST
    //   { CONTROL_PADCONF_mcbsp_clks,   MODE5,  PUPD_EN,  PULL_DOWN | INPUT_EN }, // uart1_cts // TEST
       { CONTROL_PADCONF_uart1_cts_HI,  MODE0,  PUPD_EN,  PULL_DOWN | INPUT_EN } // uart1_rx
    };

    static const PIN_CONFIG  uart2_pin_mux[]={
       { CONTROL_PADCONF_uart2_cts,   MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN }, // uart2_cts
       { CONTROL_PADCONF_uart2_cts_HI,  MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN }, // uart2_rts
       { CONTROL_PADCONF_uart2_tx,   MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN }, // uart2_tx
       { CONTROL_PADCONF_uart2_tx_HI,  MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN } // uart2_rx
    };

    static const PIN_CONFIG  uart3_pin_mux[]={
       { CONTROL_PADCONF_mcbsp1_clkx_HI, MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN }, // uart3_cts_rctx
       { CONTROL_PADCONF_uart3_rts_sd,  MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN }, // uart3_rts_sd
       { CONTROL_PADCONF_uart3_rts_sd_HI, MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN }, // uart3_rx_irrx
       { CONTROL_PADCONF_uart3_tx_irtx,  MODE0,  PUPD_EN,  PULL_UP   | INPUT_EN } // uart3_tx_irtx
    };

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    I'm sorry, but we don't have the LogicPD schematics so I have no way to check is something on the board causes this.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hi Biser,

    I tell you the value of Pad Coniguration Registers by CCS. The difference is only PULLTYPESELECT0(bit4). Actually I tried the value for 0x01180118 for UART1. What do you think?

    Regards,
    Kazu

    1651 9 48002174 0 4 0
    01180118 : CONTROL_PADCONF_UART2_CTS
    01180118 : CONTROL_PADCONF_UART2_TX
    01080108 : CONTROL_PADCONF_UART1_TX
    01080108 : CONTROL_PADCONF_UART1_CTS

  • 0 in reply to Kzk
    TI__Genius 16030 points

    Hi Kazu,

    You might also check if auto-CTS is enabled.  See the Hardware Flow Control section (14.4.4.1.3.2) of the AM35x TRM.

    Regards,

    Melissa

  • 0 in reply to melissaw
    Genius 5785 points

    Hi Melissa

    Thank you for your reply. Sure. I've checked your section and 14.5.1.2.1(Hardware Flow Control Configuration). AUTO_CTS_EN(bit7) has set and the value of EFR_REG in mode B is 0x00d0 after step6. UART1 and UART2 are same value.

    Regards,
    Kazu