Dear support,
We have the same problem as descrided in the post http://e2e.ti.com/support/embedded/tirtos/f/355/p/324340/1146924.aspx#1146924
Could you please answer?
When we try to do:
Configure PLL with PLL input clk (Osc)= 20
PLL control register-DIV= 10
PLL status register -DIVSEL= 2
It shows frequncy 0 and also at boot section CPU clk frequency becomes 0.
It is leeting me to set 100Mhz when configure PLL is selected.
Could you please help us to resolve the problem
Thanks, Sabina
