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TMS320DM8168 VINx port timing issue

Roma Bhagat1
Prodigy 110 points
Other Parts Discussed in Thread: TMS320DM8168

Hello,

We are using TMS320DM8168 interfaced with a NTSC/ PAL video decoder,whose output is driven w.r.t. falling clock edge.

TMS320DM8168 samples input data w.r.t. rising clock edge.

TMS320DM8168 datasheet page 264, mentions that at 165MHz, setup time required is 3.75nsec and hold time is 0nsec.

We are getting setup time violations on this interface and would like to know following:
1) At 108MHz input clock, will setup and hold timing requirement be the same?
2) If not, then provide for 108MHz the setup and hold timing requirement values.
3) Is it possible to change VINx port sampling from rising edge to falling edge?

Pls do revert on this at the earliest.

Thanks & Regards,
Roma Bhagat

  • 0
    TI__Mastermind 43875 points

    Input setup/hold timings are static numbers and not affected by the clock frequency.

    I don't know if there is control over the sampling clock edge polarity, sorry.

    You might also consider skewing the clock trace length to give you more setup margin. Increasing your clock trace with respect to your data lines will yield about 150ps/inch, so extending the clock line and ensuring all the data lines are closely matched to other data lines will increase your setup time.

    I assume your video decoder does not have clock polarity control? Which device are you using for video decoding?

    BR,

    Steve