hi,all:
We are using PCIe interface between our DM8168 and C6678 DSP. We have configured the DM8168 as Root Complex and the C6678 as End Point.
Now, we need to enable MSI functionality(EP will send interrupt to the RC) , with the SECTION 2.13.2 of the document SPRUGS6A, I have some questions :
1、what are "pre-determined address "and "pre-determined data"? In my view,"pre-determined address" is the address of MSI_IRQ register(0x51000054 in DM8168), "pre-determined data" is for the MSI vector number, for example: 0 refers to MSI 0 interrupt, Right?
2、Is there a example about generating a msi interrupt ?
3、how to config the bar between the DM8168 and C6678 DSP , can you give me a example about the bar config ?
For example, if i want to trigger MSI interrupt 0 in RC from EP, i issue a memory write from EP to RC and the target location is the MSI_IRQ register address (0x51000054 in RC) with the vector value 0x0 (for MSI_0) as the data being written.
- In RC the bar0 register (0x51001010) is set as 0x51000000 int the drivier files at arch/arm/mach-omap2/pcie-ti81xx.c (RC driver source) .
and the four inbound region config as follow :
BAR0: 0x51000000
IB 00 : IB_BAR: 0x1 IB_START0_LO: 0x70000000 IB_START0_HI: 0x0 IB_OFFSET: 0x70000000
IB 01 : IB_BAR: 0x0 IB_START0_LO: 0x0 IB_START0_HI: 0x0 IB_OFFSET: 0x0
IB 02 : IB_BAR: 0x0 IB_START0_LO: 0x0 IB_START0_HI: 0x0 IB_OFFSET: 0x0
IB 03 : IB_BAR: 0x0 IB_START0_LO: 0x0 IB_START0_HI: 0x0 IB_OFFSET: 0x0
- In EP I use the pcieObTransCfg method with obAddrLo = 0x70000000 which calls Pcie_cfgObOffset to setp the outbound translation. (Again, I have edited what is done in the example project.)
- Then, after all initialisation on both sides, I use *((volatile uint32_t *) 0x60000054) = 0x00; to write 0x0 to the PCIe data space to trigger the RC's interrupt. (As is used to transmit data in the example project).
After the writing from EP to RC, I check if MSI0_IRQ_STATUS (0x51000104) = 0x1 on RC side, indicating the MSI0 has been triggered.
MSI0_IRQ_ENABLE_SET (0x51000108) = 0x1 as well in RC to enable MSI0 before triggering it.
but the MSI0_IRQ_STATUS and the MSI0_IRQ_ENABLE_SET both are 0x0 !
Is there anything I am missing or that I am doing wrong? I assume all the setup on the RC is correct given I can self-trigger it.
and the print of lspci -v on RC side as follows :
#./lspci -v
03:00.0 Class 0480: Device 104c:b005 (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 368
[virtual] Memory at 21800000 (32-bit, non-prefetchable) [size=1M]
Memory at 21400000 (32-bit, non-prefetchable) [size=64K]
Memory at 20000000 (32-bit, prefetchable) [size=1M]
Memory at 20100000 (32-bit, prefetchable) [size=64K]
Memory at 20120000 (32-bit, prefetchable) [size=4K]
Memory at 20110000 (32-bit, prefetchable) [size=64K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Kernel driver in use: ti6678 pcie driver
#cat /proc/iomem
00000000-00000000 : omap2-nand.0
08000000-08000003 : omap2-nand
20000000-2fffffff : pcie-nonprefetch
20000000-200fffff : ti6678_pcie_ep
20100000-2010ffff : ti6678_pcie_ep
20110000-2011ffff : ti6678_pcie_ep
20120000-20120fff : ti6678_pcie_ep
21400000-2140ffff : ti6678_pcie_ep
21800000-218fffff : ti6678_pcie_ep
.....
Thanks , xiejian.