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C665x EMIF max bandwidth

Stuart Baker
Genius 10810 points

I'm working through the datasheet with a customer on this part and since there is a lack of sequence diagrams available, I would like someone to confirm our findings.

Our findings are that the minimum cycle time for a read is 4 cycles and the minimum cycle time for a write is 3 cycles

For multiple reads to the same chip select, there is no additional cycles required between transactions, for instance 4 reads should take 16 total cycles.

For multiple writes to the same chip select, there is no additional cycles required between transactions, for instance 4 writes should take 12 total cycles.

For writes followed by reads, reads followed by writes, or accesses to different chip selects, a turnaround penalty is incurred.

Please confirm my assertions above.

Thanks,

Stuart

  • 0
    TI__Genius 10810 points

    Could someone please comment on this?

    Thanks,

    Stuart

  • 0 in reply to Stuart Baker
    TI__Mastermind 42545 points

    Hi Stuart,

    You have stated the minimum programmable clock cycles for each type of access but that doesn't reflect the possible throughput for the EMIF interface. EMIF16 was provided as a solution for access to asynchronous memory and was specifically targeted at NOR flash for boot and NAND flash for bulk storage. It was not designed as a streaming data interface. Because of this, the data path within the device is not optimize to operate at the speeds that you have defined. Your read pulses may be four cycles but there will be numerous cycles between each read. There have been a number of threads discussing optimization for higher throughput but do not expect to string eight reads in 32 cycles. More information can be found at the following thread.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/192245.aspx

    Regards, Bill

  • 0 in reply to Bill Taboada
    TI__Genius 10810 points

    Bill,

    I've updated the customer with this information.  We are now looking at the uPP peripheral as a way to get increased throughput.  Can you provide any guidance as to what the bandwidth limitations for the uPP peripheral are?

    Thanks,

    Stuart

  • 0 in reply to Stuart Baker
    TI__Mastermind 20790 points

    Stuart,

    For UPP: The theoretical throughput is 150MB/s, the actual achievable sustained throughput do to overhead is 120MB/s.  It will operate continuously at 75MHz on the Keystone devices.