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C6746 wake up problem

Other Parts Discussed in Thread: AM1808

Hi

One of my customer has a wake up problem on C6746 out of deep sleep. They've selected following crystal Quartz ABMM2-24.000MHZ-E2-T : ESR max=50ohms, CL=18pF. They've defined C1 and C2 by using following formula Cload=(C1*C2)/(C1+C2).

Depending on the values of C1 and C2, the C6746 does not always start. They've observed in reset state ~20mA @ 5V; or USB is partially functional « surprise removal » but the behaviour differs from one board to the other.

Also the temeprature has an influence. If the crystal or C6746 is heated (air flow), wake up works well.

Test results based on C1,C2:

C1=C2=36pF                                       fail

C1=C2=20pF                                       fail

C1=C2=10pF                                       fail

C1=not mounted C2=10pF               pass

C1=C2=4.7pF                                      pass

C1=C2=not mounted                        pass

Any suggestion for selecting C1/C2 values or reference schematics? They've based the design on TRM suggestions.

Thanks,

Vincent

  • Vincent

    We have seen 1 or 2 reports from AM18xx customers (ARM only variant of this family) where there were start up issues with the crystal , mostly during power on reset.

    It is interesting that your customer only sees the issue with deep sleep suspend/resume.

    I think in both cases it was a crystal quality issue. I am digging further. Have they tried to replace the crystal or do a swap to see if the issue follows the device, crystal or board etc

    In those debugs it was mentioned that temperature dependies are possible due your capacitors are affected by temperature.  Please check your capacitors – here is some information on capacitors:      www.atceramics.com/Userfiles/temp_coef.pdf

    There was also a recommendation to make sure that the ESR is as per the spec

    Paul Eaves mentioned a way to measure that for a crystal.

    Has the customer confirmed the actual crystals installed on systems exhibiting this behavior have an ESR less than the requirements defined in the AM1808 data sheet?  If not, they should remove a few crystals from systems with this issue and measure the crystal ESR.

     

    This can be done by connecting one terminal of the crystal being measured to the output of a signal generator and the other terminal to a known resistor (20 – 50 ohms) which is connected to the signal generator ground, then measure the voltage across the known resistor and output of the signal generator while tuned to the resonant frequency of the crystal.  This will allow you calculate the actual ESR of the crystal by comparing the voltage drop across the known resistor with the voltage drop across the crystal.

     

    The ESR of the crystal will decrease to its lowest value and there will be a very sharp response as you tune the frequency of the signal generator across the resonant frequency of the crystal.  So you must use a signal generator than provides very precise frequency control to allow the output to be tuned to the resonant frequency of the crystal.  Make sure you adjust the voltage output of the signal generator such that it does not over-drive the crystal.

     

    You should start by adjusting the open-circuit output voltage of the signal generator between 1 - 2 volts peak-to-peak when tuned to a frequency near the resonant frequency of the crystal.  Connect the crystal circuit as described above and monitor the voltage across the known resistor and output of the signal generator with separate scope traces, look for the voltage across the known resistor to peak and the voltage of the signal generator dip suddenly as you tune across the resonant frequency of the crystal which should occur near the specified frequency of the crystal.  Once you are tuned to resonant frequency of the crystal, measure the two voltages.  The ESR of the crystal can be calculated with the following equation.

     

    ESR = [(Rkr * (Vsg – Vkr)) / Vkr]

    where Rkr is the resistance of the known resistor, Vsg is the voltage output from the signal generator, Vkr is the voltage drop across the known resistor.

  • This issue was confirmed to be resolved by adding a series resistor Rs to the cricuit)  (The resistor in series with the output of the inverter in the internal/on chip oscillator).

    These series resistors, typically allow reducing the drive strength of the crystal (attenate the signal and decrease the slew rate), as well as increase/adds to phase shift for the circuit


    We have seen the Rs to help in similar scenarios for at least 2 more customers using this device family.

    The plan is to update the OMAPL1x schematic checklist to add a recommendation to have these series resistor in the initial design/prototype phase.

    Regards

    Mukul