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C6678 SRIO SHADOW REGISTER BEHAVIOUR

Gabriele_Giannini
Intellectual 925 points

I'm noticing unexpected behavior when programming the SRIO module and i have some doubt about the shadow registers.

In my project i've taken the LOCK of the Shadow Registers of the LSU0 and i have some function for setup the LSU.registers 0-4 and another for trigger the transmission writing in the LSU register 5.
But reading via Watch Window the values in the LSU reg i found values mismatching the data i've written (For example LSU REG 4 = 0x0 whatever i've written in it.)

My doubt is: Any access to a certain LSU REG after the lock corresponds to using a new set of the shadow registers until i've them available?
Because for readability pourpose i'm using different function to write in the same shadow register using OR masking (For example i made 3 writes in LSU REG 4) while using a unique function to write the single register simultaneously i don't have this problem...

Is my assumption correct or there are some other problems?

  • 0
    TI__Mastermind 28085 points

    Hi Gabriele,

    Each LSU is a set of shadow registers. Each shadow register can be programmed for setting up a transaction ahead of time. When the LSU is free, the data is transferred from the shadow register to the LSU register. The point at which the data is actually transferred from the shadow registers to the actual LSU registers, the values of LSU0-5 registers can be read. Prior to that, a read of these registers will indicate the last value that was present in these registers. This implies that the new values cannot be read until a write to REG5 and further constrained by the fact that there is no other command ahead of the current command being setup. Reg6 can be read as and when it is written to, as it is used for locking and releasing.

    If you need more information refer SRIO user guide

    http://www.ti.com/lit/sprugw1

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 925 points

    I've readen the datasheet and of course i'm reading after the final step of my code, where i trigger the transmission writing in the LSU_REG5.

    After that step i've noticed in the registers that the values are not correct if i write multiple time in the same shadow register before triggering the transmission (for example doing a first write in the LSU_REG4 for setting SrcID and DestID and with anoter function a second write adding the interrupt setting), and the result of the transaction is not the one expected (for example a transfer of a 256 Byte struct, instead of the first 4 bytes as i had set)

    If i write every shadow reg in a single step, instead, i have the correct values when i read them after the transaction, and the result is the one expected

  • 0 in reply to Gabriele_Giannini
    TI__Mastermind 28085 points

    Hi Gabriele,

    In single write on every shadow register working means, the data is transferred from the shadow register to the LSU register properly.

    In multiple write time you make sure there is space in the Shadow registers to write. Have you refer the TI example code for this issue.

    Refer below SRIO training document for more information about shadow register

    6724.KeyStone SRIO Overview.pptx

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 925 points

    So, the point is that if the LSU0 (for example) has a set of four shadow registers and i lock it, the first write is for shadow register set 0, the second for the second set and so on?

  • 0 in reply to Gabriele_Giannini
    TI__Mastermind 28085 points

    Hi Gabriele,

    Yes, your understanding is correct.

    The total shadow registers that can be assigned to each LSU is configurable, for a total of 32 sets of registers of the total of 32 shadow register, 16 of them are used for LSU0-3, while the other 16 can only be used for LSU4-7. The total shadow registers assigned to an LSU is setup via the RIO_LSU_SETUP_REG0.

    Thanks,