insmod fpga driver

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Hi

    I am using the am3358 to design product. one nand and one fpga are in the product. I use GPMC port to access the nand and the fpga.

   /* Pin mux for nand flash module */

static struct pinmux_config nand_pin_mux[] = {
 {"gpmc_ad0.gpmc_ad0",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad1.gpmc_ad1",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad2.gpmc_ad2",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad3.gpmc_ad3",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad4.gpmc_ad4",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad5.gpmc_ad5",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad6.gpmc_ad6",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad7.gpmc_ad7",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
// {"gpmc_wpn.gpmc_wpn",   OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_oen_ren.gpmc_oen_ren",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 
 {NULL, 0},
};

/* Pin mux for fpga flash module */
static struct pinmux_config fpga_pin_mux[] = {
 {"gpmc_ad0.gpmc_ad0",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad1.gpmc_ad1",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad2.gpmc_ad2",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad3.gpmc_ad3",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad4.gpmc_ad4",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad5.gpmc_ad5",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad6.gpmc_ad6",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 {"gpmc_ad7.gpmc_ad7",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},

 {"lcd_data0.gpmc_a0",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},
 {"lcd_data1.gpmc_a1",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},
 {"lcd_data2.gpmc_a2",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},
 {"lcd_data3.gpmc_a3",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},
 {"lcd_data4.gpmc_a4",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},
 {"lcd_data5.gpmc_a5",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},
 {"lcd_data6.gpmc_a6",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},
 {"lcd_data7.gpmc_a7",   OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT|AM33XX_PULL_DISA},

 {"gpmc_csn1.gpmc_csn1",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_oen_ren.gpmc_oen_ren",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 {NULL, 0},
};

Begining,i don't use the nand. all the program is in the SD card.

I input this command in the linux

root@am335x-evm:~# mount /dev/mmcblk0p1 /mnt/card/

root@am335x-evm:~# cd /mnt/card/

root@am335x-evm:/media/card# ls
MLO         fpga.ko     fpga_test   u-boot.img  uImage     

root@am335x-evm:/media/card# insmod fpga.ko

root@am335x-evm:/media/card# ./fpga_test

the am3358 can access the fpga successfully.

the second, i flashed the MLO u-boot.img uImage ubi.img fpga.ko and fpga_test in the nand

the linux can work in the nand

but when i use the same command

insmod fpga.ko

there many error in the terminal

am335x-evm login: root
root@am335x-evm:~# cd /app/
root@am335x-evm:/app# insmod fpga.ko 
[ 2241.860259] Disabling lock debugging due to kernel taint
[ 2241.866555] GPMC revision 6.0
[ 2241.869663] Got CS1, address = 1000000
[ 2241.873695] fpga_base d1000000
root@am335x-evm:/app# [ 2243.576425] Unhandled fault: external abort on non-linefetch (0x1008) at 0xd083a000
[ 2243.584434] Internal error: : 1008 [#1]
[ 2243.588430] Modules linked in: fpga(O)
[ 2243.592354] CPU: 0 Tainted: G W O (3.2.0 #19)
[ 2243.598001] PC is at nand_read_byte+0x14/0x20
[ 2243.602544] LR is at nand_check_wp+0x48/0x58
[ 2243.606996] pc : [<c024d8d0>] lr : [<c024db4c>] psr: 60000013
[ 2243.607003] sp : cfaefcf8 ip : cfaefd08 fp : cfaefd04
[ 2243.618969] r10: 000007ff r9 : 00000000 r8 : 03926800
[ 2243.624414] r7 : cf9a4a28 r6 : 00000800 r5 : cf9a4810 r4 : cf9a4a28
[ 2243.631219] r3 : d083a000 r2 : 00000081 r1 : ffffffff r0 : cf9a4810
[ 2243.638027] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
[ 2243.645647] Control: 10c5387d Table: 8f180019 DAC: 00000015
[ 2243.651638] Process ubifs_bgt0_0 (pid: 709, stack limit = 0xcfaee2f0)
[ 2243.658353] Stack: (0xcfaefcf8 to 0xcfaf0000)
[ 2243.662894] fce0: cfaefd1c cfaefd08
[ 2243.671425] fd00: c024db4c c024d8c8 cfaefd98 cf9a4810 cfaefd8c cfaefd20 c0251420 c024db10
[ 2243.679956] fd20: 00000000 00000001 bafffffd 60000013 00000000 00000000 00000000 00000000
[ 2243.688486] fd40: cfaeb800 000003b6 cfaefd74 00000040 e9ba7fad cfaeb800 03926800 00000000
[ 2243.697017] fd60: 00000000 cf9a4810 00000800 03926800 00000000 00000000 cfaeb800 000003b6
[ 2243.705548] fd80: cfaefdd4 cfaefd90 c0251890 c0251354 cfaefd98 ee4abfd2 00000000 00000800
[ 2243.714078] fda0: 00000000 e9ba7fad b19feba7 a5fefcaf cfaeb800 00000000 00780000 00000000
[ 2243.722609] fdc0: 031a7000 00000000 cfaefe04 cfaefdd8 c0244d6c c0251810 00000800 cfaefe1c
[ 2243.731140] fde0: cfaeb800 cf195c80 00006800 0000018d cfaefe1c 00000800 cfaefe3c cfaefe08
[ 2243.739671] fe00: c026504c c0244d0c 00000800 cfaefe1c cfaeb800 cfaefe20 c0376994 c037726c
[ 2243.748202] fe20: cf9a4000 0000018d 00005800 00000800 cfaefedc cfaefe40 c0263370 c0265000
[ 2243.756733] fe40: 00000800 fb8fefee ba375ddb cfc0ffff d7dfff7f 5ff954c7 fff7fbb9 fddbddbf
[ 2243.765264] fe60: 7b9b4bff cff37fdf de7eb957 bfad39e7 afcffbbf fddfee4f bff73bf7 b5fffd7f
[ 2243.773795] fe80: ff77bf45 7eee77fe 6edf7f53 fd676d5b acf9edf9 77fabfff a7f3a2ff dbbbfebc
[ 2243.782326] fea0: ff9b279b f8af1faf 0000169f 00000000 3f5f1bf1 000003b6 cfaeb800 00000800
[ 2243.790856] fec0: 00000002 00000080 00000000 cfaa6358 cfaeff14 cfaefee0 c02625bc c02632f8
[ 2243.799387] fee0: 00005800 00000800 00000002 c0036f0c c0038fa0 cfaae000 cfaae000 000003b6
[ 2243.807919] ff00: 00005800 00000800 cfaeff4c cfaeff18 c017418c c02624c8 00000800 00000002
[ 2243.816450] ff20: cfaeff4c cfaeff30 c01746e8 cfaa6330 cfaae000 00000800 000007c0 00000002
[ 2243.824982] ff40: cfaeff74 cfaeff50 c01749b4 c0174140 00000800 00000002 cfaae000 00000001
[ 2243.833513] ff60: cfaa6330 00000130 cfaeff9c cfaeff78 c0174ba8 c0174930 cfaae000 cfaee000
[ 2243.842043] ff80: 00000001 cfaae18c 00000000 00000000 cfaeffbc cfaeffa0 c017d148 c0174ae4
[ 2243.850574] ffa0: cf81dd58 cfaae000 c017d0b4 00000013 cfaefff4 cfaeffc0 c0055d48 c017d0c0
[ 2243.859104] ffc0: cf81dd58 00000000 cfaae000 00000000 cfaeffd0 cfaeffd0 00000000 cf81dd58
[ 2243.867634] ffe0: c0055cb8 c00404a4 00000000 cfaefff8 c00404a4 c0055cc4 d8deebf4 edf760b7
[ 2243.876157] Backtrace: 
[ 2243.878718] [<c024d8bc>] (nand_read_byte+0x0/0x20) from [<c024db4c>] (nand_check_wp+0x48/0x58)
[ 2243.887710] [<c024db04>] (nand_check_wp+0x0/0x58) from [<c0251420>] (nand_do_write_ops+0xd8/0x3bc)
[ 2243.897049] r5:cf9a4810 r4:cfaefd98
[ 2243.900789] [<c0251348>] (nand_do_write_ops+0x0/0x3bc) from [<c0251890>] (nand_write+0x8c/0xa8)
[ 2243.909865] [<c0251804>] (nand_write+0x0/0xa8) from [<c0244d6c>] (part_write+0x6c/0x8c)
[ 2243.918208] r7:00000000 r6:031a7000 r5:00000000 r4:00780000
[ 2243.924137] [<c0244d00>] (part_write+0x0/0x8c) from [<c026504c>] (ubi_io_write+0x58/0xb4)
[ 2243.932661] r7:00000800 r6:cfaefe1c r5:0000018d r4:00006800
[ 2243.938584] [<c0264ff4>] (ubi_io_write+0x0/0xb4) from [<c0263370>] (ubi_eba_write_leb+0x84/0x828)
[ 2243.947832] r7:00000800 r6:00005800 r5:0000018d r4:cf9a4000
[ 2243.953754] [<c02632ec>] (ubi_eba_write_leb+0x0/0x828) from [<c02625bc>] (ubi_leb_write+0x100/0x104)
[ 2243.963297] [<c02624bc>] (ubi_leb_write+0x0/0x104) from [<c017418c>] (ubifs_leb_write+0x58/0xa4)
[ 2243.972455] r8:00000800 r7:00005800 r6:000003b6 r5:cfaae000 r4:cfaae000
[ 2243.979471] [<c0174134>] (ubifs_leb_write+0x0/0xa4) from [<c01749b4>] (ubifs_wbuf_sync_nolock+0x90/0x134)
[ 2243.989444] r8:00000002 r7:000007c0 r6:00000800 r5:cfaae000 r4:cfaa6330
[ 2243.996460] [<c0174924>] (ubifs_wbuf_sync_nolock+0x0/0x134) from [<c0174ba8>] (ubifs_bg_wbufs_sync+0xd0/0x170)
[ 2244.006887] r7:00000130 r6:cfaa6330 r5:00000001 r4:cfaae000
[ 2244.012812] [<c0174ad8>] (ubifs_bg_wbufs_sync+0x0/0x170) from [<c017d148>] (ubifs_bg_thread+0x94/0x120)
[ 2244.022624] [<c017d0b4>] (ubifs_bg_thread+0x0/0x120) from [<c0055d48>] (kthread+0x90/0x94)
[ 2244.031239] r7:00000013 r6:c017d0b4 r5:cfaae000 r4:cf81dd58
[ 2244.037171] [<c0055cb8>] (kthread+0x0/0x94) from [<c00404a4>] (do_exit+0x0/0x67c)
[ 2244.044970] r6:c00404a4 r5:c0055cb8 r4:cf81dd58
[ 2244.049798] Code: e92dd800 e24cb004 e59030cc e5933000 (e5d30000) 
[ 2244.056213] ---[ end trace 1b75b31a2719ed21 ]---

I don't know the reason?

thanks, can you help me to solve this question.

I have asked a software expert to look at this.

Hi Xiangzhen,

My assumption, from looking at the ubi related errors in your log, is that in your second use-case (booting from NAND), your root file system is located on the NAND flash, and when inserting the fpga.ko module, both the NAND flash and the FPGA are trying to access / to be accessed from the GPMS bus and something similar to a race condition is happening.

In order to verify or dismiss my theory please try to boot from NAND, but modify the U-Boot environment variables to use the root file system from the MMC/SD card as in your first use-case and let's see if the kernel will still crash when inserting the fpga.ko module.

Best regards,
Miroslav

thanks for your answer,i have find the question in my fpga driver.

in my fpga driver,it have this commands

 gpmc_write_reg(GPMC_SYSCONFIG, 0xA);
 while((gpmc_read_reg(GPMC_SYSSTATUS) & 0x0001) == 0){
  printk("GPMC reset is not end\n");
 }

the purpose's of this command is to reset the CPMC,when i use this driver in my first use-case(booting from SD),it is not conflict with nand.But when i boot from nand,it will conflict with nand.

But i find anthor question today.I program like this

 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG1, gpmc_nor[0]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG2, gpmc_nor[1]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG3, gpmc_nor[2]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG4, gpmc_nor[3]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG5, gpmc_nor[4]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG6, gpmc_nor[5]);

 
if (gpmc_cs_request(GPMC_CS, SZ_64K, (unsigned long *)&mem_base) < 0){
  printk(KERN_ERR "Failed request for GPMC mem for usrp_e\n");
  return -1;
 }
 printk("Got CS1, address = %lx\n", mem_base);

 if (!request_mem_region(mem_base, SZ_64K, "mem_fpga")) {
  printk(KERN_ERR "Request_mem_region failed.\n");
  gpmc_cs_free(GPMC_CS);
  return -1;
 }

 fpga_base = ioremap(mem_base, SZ_64K);
 printk("fpga_base %p\n",fpga_base);

I use this program to receive the base address of fpga,but when i use write() to write data to fpga,i find the fpga_base is not the base address of the ram in the fpga(I design the ram in the fpga,the arm can access to the ram by using gpmc interface).When i write data to the fpga_base,the data is writed to the 0x2001 address of the ram in the fpga.I think it will be writed to the 0x0 address of ram in the fpga.

I don't know the reason,please help me.

thank you very much.

Hi

    The first problem i have solved. But i have another problem like this

I program like this

 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG1, gpmc_nor[0]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG2, gpmc_nor[1]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG3, gpmc_nor[2]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG4, gpmc_nor[3]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG5, gpmc_nor[4]);
 gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG6, gpmc_nor[5]);

 
if (gpmc_cs_request(GPMC_CS, SZ_64K, (unsigned long *)&mem_base) < 0){
  printk(KERN_ERR "Failed request for GPMC mem for usrp_e\n");
  return -1;
 }
 printk("Got CS1, address = %lx\n", mem_base);

 if (!request_mem_region(mem_base, SZ_64K, "mem_fpga")) {
  printk(KERN_ERR "Request_mem_region failed.\n");
  gpmc_cs_free(GPMC_CS);
  return -1;
 }

 fpga_base = ioremap(mem_base, SZ_64K);
 printk("fpga_base %p\n",fpga_base);

I use this program to receive the base address of fpga,but when i use write() to write data to fpga,i find the fpga_base is not the base address of the ram in the fpga(I design the ram in the fpga,the arm can access to the ram by using gpmc interface).When i write data to the fpga_base,the data is writed to the 0x2001 address of the ram in the fpga.I think it will be writed to the 0x0 address of ram in the fpga.

I don't know the reason,please help me.

thank you very much.